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arm.c (use_return_insn): Do not use a single return instruction for interrupt handelrs which have to...
* config/arm/arm.c (use_return_insn): Do not use a single return instruction for interrupt handelrs which have to create a stack frame. (arm_expand_prologue): Do not pre-bias the return address of interrupt handlers which create a stack frame. From-SVN: r61698
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@ -1,3 +1,53 @@
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2003-01-24 Nick Clifton <nickc@redhat.com>
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* config/arm/arm.c (use_return_insn): Do not use a single return
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instruction for interrupt handelrs which have to create a stack
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frame.
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(arm_expand_prologue): Do not pre-bias the return address of
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interrupt handlers which create a stack frame.
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2003-01-24 Nick Clifton <nickc@redhat.com>
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* Add sh2e support:
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2002-08-12 Alexandre Oliva <aoliva@redhat.com>
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* config/sh/sh.c (output_branch) [TARGET_SH2E]: Handle
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med_cbranches. Fix logic in short_cbranches.
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2002-04-03 Alexandre Oliva <aoliva@redhat.com>
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* config/sh/sh.md (delay for cbranch): Don't annul delay
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slots on SH2e.
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* config/sh/sh.c (sh_insn_length_adjustment): Add 2 for
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cbranch with unfilled delay slot on SH2e.
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(output_branch): Fill with a nop the delay slot of a
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branch that required a delay slot but didn't get one.
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2002-04-02 Alexandre Oliva <aoliva@redhat.com>
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* doc/invoke.texi (SH options): Document -m2e.
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* config/sh/crt1.asm: Add __SH2E__ Next to __SH3E__.
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* config/sh/lib1funcs.asm: Likewise.
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* config/sh/sh.c: Replace all uses of TARGET_SH3E with SH2E.
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* config/sh/sh.h (CPP_SPEC): Define __SH2E__ for -m2e, and
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not __sh1__.
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(CONDITIONAL_REGISTER_USAGE): Don't disable FP regs from
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SH2E up.
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(SH3E_BIT): Renamed to...
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(SH_E_BIT): ... this. Replace all uses.
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(TARGET_SH2E): Define from SH_E_BIT and TARGET_SH2.
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Replace all uses of TARGET_SH3E with TARGET_SH2E.
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(TARGET_SWITCHES): Added 2e.
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(OVERRIDE_OPTIONS): Set sh_cpu for SH2E.
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(processor_type): Added PROCESSOR_SH2E.
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* config/sh/sh.md: Replace all uses of TARGET_SH3E with
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TARGET_SH2E, except in sqrtsf2_i.
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(attribute cpu): Added sh2e.
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* config/sh/t-sh (MULTILIB_OPTIONS): Replace m3e with m2e.
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(MULTILIB_MATCHES): Use m2e multilib for m3e.
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* config.gcc: Add sh2e target support.
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2003-01-24 Phil Edwards <pme@gcc.gnu.org>
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Rename -W to -Wextra.
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@ -938,6 +938,10 @@ use_return_insn (iscond)
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consideration. */
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if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
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return 0;
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/* So do interrupt functions that use the frame pointer. */
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if (IS_INTERRUPT (func_type) && frame_pointer_needed)
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return 0;
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/* As do variadic functions. */
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if (current_function_pretend_args_size
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@ -7092,7 +7096,7 @@ output_move_double (operands)
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{
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if (GET_CODE (otherops[2]) == CONST_INT)
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{
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switch (INTVAL (otherops[2]))
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switch ((int) INTVAL (otherops[2]))
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{
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case -8:
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output_asm_insn ("ldm%?db\t%1, %M0", otherops);
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@ -7168,7 +7172,7 @@ output_move_double (operands)
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case PLUS:
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if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
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{
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switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
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switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
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{
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case -8:
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output_asm_insn ("stm%?db\t%m0, %M1", operands);
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@ -8813,18 +8817,19 @@ arm_expand_prologue ()
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RTX_FRAME_RELATED_P (insn) = 1;
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}
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/* If this is an interrupt service routine, and the link register is
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going to be pushed, subtracting four now will mean that the
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function return can be done with a single instruction. */
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/* If this is an interrupt service routine, and the link register
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is going to be pushed, and we are not creating a stack frame,
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(which would involve an extra push of IP and a pop in the epilogue)
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subtracting four from LR now will mean that the function return
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can be done with a single instruction. */
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if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
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&& (live_regs_mask & (1 << LR_REGNUM)) != 0)
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{
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emit_insn (gen_rtx_SET (SImode,
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gen_rtx_REG (SImode, LR_REGNUM),
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gen_rtx_PLUS (SImode,
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gen_rtx_REG (SImode, LR_REGNUM),
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GEN_INT (-4))));
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}
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&& (live_regs_mask & (1 << LR_REGNUM)) != 0
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&& ! frame_pointer_needed)
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emit_insn (gen_rtx_SET (SImode,
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gen_rtx_REG (SImode, LR_REGNUM),
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gen_rtx_PLUS (SImode,
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gen_rtx_REG (SImode, LR_REGNUM),
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GEN_INT (-4))));
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if (live_regs_mask)
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{
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