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h8300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV.
* h8300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV.
(shift_one, shift_two): Set CC_NO_CARRY as needed. Remove
references to CC_OVERFLOW_0.
(emit_a_shift): Similarly.
* h8300.h (CC_OVERFLOW_0): Remove.
* h8300.md: Use set_zn and set_znv for cc0 tracking.
(bCC): Restore the comparison is CC_OVERFLOW_UNUSABLE is set and
the comparison needs the overflow bits.
From-SVN: r14020
This commit is contained in:
Jeff Law
parent
d116300be8
commit
065bbfe6bf
@ -1597,15 +1597,7 @@ notice_update_cc (body, insn)
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cc_status.value1 = 0;
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break;
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case CC_SET:
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/* Insn sets the Z,N,V flags of CC to recog_operand[0].
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C may or may not be set to 0 but that's ok
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because alter_cond will change tests to use EQ/NE. */
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CC_STATUS_INIT;
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cc_status.value1 = recog_operand[0];
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break;
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case CC_SET_ZN_C0:
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case CC_SET_ZN:
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/* Insn sets the Z,N flags of CC to recog_operand[0].
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The V flag is unusable. The C flag may or may not be known but
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that's ok because alter_cond will change tests to use EQ/NE. */
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@ -1614,6 +1606,15 @@ notice_update_cc (body, insn)
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cc_status.value1 = recog_operand[0];
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break;
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case CC_SET_ZNV:
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/* Insn sets the Z,N,V flags of CC to recog_operand[0].
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The C flag may or may not be known but that's ok because
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alter_cond will change tests to use EQ/NE. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_NO_CARRY;
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cc_status.value1 = recog_operand[0];
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break;
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case CC_COMPARE:
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/* The insn is a compare instruction. */
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CC_STATUS_INIT;
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@ -1907,13 +1908,13 @@ static const struct shift_insn shift_one[2][3][3] =
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{
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/* SHIFT_ASHIFT */
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{
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{ "shll\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shll\t%X0", CC_NO_CARRY },
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{ "add.w\t%T0,%T0", CC_OVERFLOW_UNUSABLE | CC_NO_CARRY },
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{ "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", 0 }
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},
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/* SHIFT_LSHIFTRT */
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{
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{ "shlr\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shlr\t%X0", CC_NO_CARRY },
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{ "shlr\t%t0\n\trotxr\t%s0", 0 },
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{ "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", 0 }
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},
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@ -1928,15 +1929,15 @@ static const struct shift_insn shift_one[2][3][3] =
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{
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/* SHIFT_ASHIFT */
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{
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{ "shll.b\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shll.w\t%T0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shll.l\t%S0", CC_OVERFLOW_0 | CC_NO_CARRY }
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{ "shll.b\t%X0", CC_NO_CARRY },
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{ "shll.w\t%T0", CC_NO_CARRY },
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{ "shll.l\t%S0", CC_NO_CARRY }
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},
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/* SHIFT_LSHIFTRT */
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{
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{ "shlr.b\t%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shlr.w\t%T0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shlr.l\t%S0", CC_OVERFLOW_0 | CC_NO_CARRY }
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{ "shlr.b\t%X0", CC_NO_CARRY },
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{ "shlr.w\t%T0", CC_NO_CARRY },
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{ "shlr.l\t%S0", CC_NO_CARRY }
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},
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/* SHIFT_ASHIFTRT */
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{
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@ -1951,15 +1952,15 @@ static const struct shift_insn shift_two[3][3] =
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{
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/* SHIFT_ASHIFT */
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{
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{ "shll.b\t#2,%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shll.w\t#2,%T0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shll.l\t#2,%S0", CC_OVERFLOW_0 | CC_NO_CARRY }
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{ "shll.b\t#2,%X0", CC_NO_CARRY },
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{ "shll.w\t#2,%T0", CC_NO_CARRY },
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{ "shll.l\t#2,%S0", CC_NO_CARRY }
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},
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/* SHIFT_LSHIFTRT */
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{
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{ "shlr.b\t#2,%X0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shlr.w\t#2,%T0", CC_OVERFLOW_0 | CC_NO_CARRY },
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{ "shlr.l\t#2,%S0", CC_OVERFLOW_0 | CC_NO_CARRY }
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{ "shlr.b\t#2,%X0", CC_NO_CARRY },
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{ "shlr.w\t#2,%T0", CC_NO_CARRY },
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{ "shlr.l\t#2,%S0", CC_NO_CARRY }
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},
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/* SHIFT_ASHIFTRT */
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{
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@ -2658,7 +2659,7 @@ emit_a_shift (insn, operands)
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sprintf (insn_buf, "and #%d,%%X0",
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mask, n);
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cc_status.value1 = operands[0];
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cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY;
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cc_status.flags |= CC_NO_CARRY;
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break;
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case HImode:
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sprintf (insn_buf, "and #%d,%%s0\n\tand #%d,%%t0",
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@ -2674,7 +2675,7 @@ emit_a_shift (insn, operands)
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"bwl"[shift_mode], mask,
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mode == QImode ? 'X' : mode == HImode ? 'T' : 'S');
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cc_status.value1 = operands[0];
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cc_status.flags |= CC_OVERFLOW_0 | CC_NO_CARRY;
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cc_status.flags |= CC_NO_CARRY;
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}
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output_asm_insn (insn_buf, operands);
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return "";
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@ -999,8 +999,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
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#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
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/* The mov,and,or,xor insns always set V to 0. */
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#define CC_OVERFLOW_0 0400
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/* The add insns don't set overflow in a usable way. */
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#define CC_OVERFLOW_UNUSABLE 01000
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/* The mov,and,or,xor insns don't set carry. That's ok though as the
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@ -1009,7 +1007,6 @@ h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
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CC_NO_OVERFLOW defined for this purpose. Rename it to something more
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understandable. */
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#define CC_NO_CARRY CC_NO_OVERFLOW
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/* ??? Use CC_Z_IN_NOT_C for bld insns? */
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/* Control the assembler format that we output. */
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@ -86,13 +86,11 @@
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;; none_0hit - insn does not affect cc but it does modify operand 0
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;; This attribute is used to keep track of when operand 0 changes.
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;; See the description of NOTICE_UPDATE_CC for more info.
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;; set - insn sets flags z,n,v. c are set to 0.
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;; (c may not really be set to 0 but that's ok, we don't need it anyway).
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;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
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;; be known (if it isn't that's ok, we don't need it anyway).
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;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
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;; set_zn - insn sets z,n to usable values; v,c are unknown.
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;; compare - compare instruction
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;; clobber - value of cc is unknown
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(define_attr "cc" "none,none_0hit,set,set_zn_c0,compare,clobber"
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(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
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(const_string "clobber"))
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;; ----------------------------------------------------------------------
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@ -113,7 +111,7 @@
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return \"push.l %S1\";
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}"
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[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (match_operand:QI 0 "general_operand_dst" "=r,r,<,r,r,m")
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@ -131,7 +129,7 @@
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[(const_int 2) (const_int 2) (const_int 2) (const_int 2)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand_dst" "")
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@ -159,7 +157,7 @@
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[(set_attr_alternative "length"
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[(const_int 2) (const_int 2) (const_int 2)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
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;; movhi
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@ -177,7 +175,7 @@
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return \"push.l %S1\";
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}"
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[(set (attr "length") (if_then_else (eq_attr "cpu" "h8300") (const_int 2) (const_int 4)))
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
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@ -195,7 +193,7 @@
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[(const_int 2) (const_int 2) (const_int 2) (const_int 4)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand_dst" "")
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@ -223,7 +221,7 @@
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[(set_attr_alternative "length"
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[(const_int 2) (const_int 2) (const_int 4)
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(if_then_else (eq_attr "cpu" "h8300") (const_int 4) (const_int 8))])
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv")])
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;; movsi
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@ -440,7 +438,7 @@
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return \"mov.l %S1,%S0\";
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}"
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[(set_attr "length" "2,2,10,10,4,4,2,6,4")
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,none_0hit,none_0hit,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
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(define_insn "movsf_h8300h"
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[(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
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@ -456,7 +454,7 @@
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mov.l %S1,%S0
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mov.l %S1,%S0"
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[(set_attr "length" "2,2,10,10,4,4")
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(set_attr "cc" "set,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0,set_zn_c0")])
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(set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
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;; ----------------------------------------------------------------------
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;; TEST INSTRUCTIONS
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@ -469,7 +467,7 @@
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""
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"btst %Z1,%R0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn ""
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[(set (cc0) (zero_extract:HI (match_operand:QI 0 "bit_memory_operand" "rU")
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@ -478,7 +476,7 @@
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn ""
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[(set (cc0) (zero_extract:SI (match_operand:QI 0 "bit_memory_operand" "rU")
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@ -487,7 +485,7 @@
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn ""
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[(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r")
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@ -496,7 +494,7 @@
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""
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"btst %Z1,%R0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn ""
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[(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r")
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@ -505,7 +503,7 @@
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn ""
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[(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r")
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@ -514,28 +512,28 @@
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""
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"btst %Z1,%Y0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_zn")])
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(define_insn "tstqi"
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[(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
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""
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"mov.b %X0,%X0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_znv")])
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(define_insn "tsthi"
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[(set (cc0) (match_operand:HI 0 "register_operand" "r"))]
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""
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"mov.w %T0,%T0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_znv")])
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(define_insn "tstsi"
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[(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
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"TARGET_H8300H || TARGET_H8300S"
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"mov.l %S0,%S0"
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[(set_attr "length" "2")
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(set_attr "cc" "set_zn_c0")])
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(set_attr "cc" "set_znv")])
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(define_insn "cmpqi"
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[(set (cc0)
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@ -597,7 +595,7 @@
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""
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"add.b %X2,%X0"
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[(set_attr "length" "2")
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn")])
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(define_expand "addhi3"
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[(set (match_operand:HI 0 "register_operand" "")
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@ -631,7 +629,7 @@
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add.w %T2,%T0
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mov.w %T1,%T0\;add.w %T2,%T0"
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[(set_attr "length" "4,2,6")
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(set_attr "cc" "clobber,set,set")])
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(set_attr "cc" "clobber,set_zn,set_zn")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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@ -642,7 +640,7 @@
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add.w %T2,%T0
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add.w %T2,%T0"
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[(set_attr "length" "4,2")
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(set_attr "cc" "set,set")])
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(set_attr "cc" "set_zn,set_zn")])
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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@ -687,7 +685,7 @@
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add.l %S2,%S0
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add.l %S2,%S0"
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[(set_attr "length" "6,2")
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(set_attr "cc" "set,set")])
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(set_attr "cc" "set_zn,set_zn")])
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;; ----------------------------------------------------------------------
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;; SUBTRACT INSTRUCTIONS
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@ -702,7 +700,7 @@
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sub.b %X2,%X0
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add.b %G2,%X0"
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[(set_attr "length" "2")
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(set_attr "cc" "set")])
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(set_attr "cc" "set_zn")])
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(define_expand "subhi3"
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[(set (match_operand:HI 0 "register_operand" "")
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@ -740,7 +738,7 @@
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sub.w %T2,%T0
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add.b %E2,%s0\;addx %F2,%t0"
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[(set_attr "length" "2,4")
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(set_attr "cc" "set,clobber")])
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(set_attr "cc" "set_zn,clobber")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=r,&r")
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@ -751,7 +749,7 @@
|
||||
sub.w %T2,%T0
|
||||
sub.w %T2,%T0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set,set")])
|
||||
(set_attr "cc" "set_zn,set_zn")])
|
||||
|
||||
(define_expand "subsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
@ -798,7 +796,7 @@
|
||||
sub.l %S2,%S0
|
||||
sub.l %S2,%S0"
|
||||
[(set_attr "length" "2,6")
|
||||
(set_attr "cc" "set,set")])
|
||||
(set_attr "cc" "set_zn,set_zn")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; MULTIPLY INSTRUCTIONS
|
||||
@ -813,7 +811,7 @@
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"mulxs.b %X2,%T0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
(define_insn "mulhisi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
@ -822,7 +820,7 @@
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"mulxs.w %T2,%S0"
|
||||
[(set_attr "length" "4")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
(define_insn "umulqihi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -985,7 +983,7 @@
|
||||
and %X2,%X0
|
||||
bclr %W2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
(set_attr "cc" "set_znv,none_0hit")])
|
||||
|
||||
(define_expand "andqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "")
|
||||
@ -1089,7 +1087,7 @@
|
||||
or %X2,%X0
|
||||
bset %V2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
(set_attr "cc" "set_znv,none_0hit")])
|
||||
|
||||
(define_expand "iorqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "=r,U")
|
||||
@ -1175,7 +1173,7 @@
|
||||
xor %X2,%X0
|
||||
bnot %V2,%R0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,none_0hit")])
|
||||
(set_attr "cc" "set_znv,none_0hit")])
|
||||
|
||||
(define_expand "xorqi3"
|
||||
[(set (match_operand:QI 0 "bit_operand" "=r,U")
|
||||
@ -1258,7 +1256,7 @@
|
||||
""
|
||||
"neg %X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
(define_expand "neghi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -1288,7 +1286,7 @@
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"neg %T0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
(define_expand "negsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
@ -1318,7 +1316,7 @@
|
||||
"TARGET_H8300H || TARGET_H8300S"
|
||||
"neg %S0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_zn")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; NOT INSTRUCTIONS
|
||||
@ -1330,7 +1328,7 @@
|
||||
""
|
||||
"not %X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
(define_insn "one_cmplhi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
@ -1474,6 +1472,16 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
|
||||
&& (GET_CODE (operands[1]) == GT
|
||||
|| GET_CODE (operands[1]) == GE
|
||||
|| GET_CODE (operands[1]) == LE
|
||||
|| GET_CODE (operands[1]) == LT))
|
||||
{
|
||||
cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (get_attr_length (insn) == 2)
|
||||
return \"b%j1 %l0\";
|
||||
else if (get_attr_length (insn) == 4)
|
||||
@ -1493,6 +1501,16 @@
|
||||
""
|
||||
"*
|
||||
{
|
||||
if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
|
||||
&& (GET_CODE (operands[1]) == GT
|
||||
|| GET_CODE (operands[1]) == GE
|
||||
|| GET_CODE (operands[1]) == LE
|
||||
|| GET_CODE (operands[1]) == LT))
|
||||
{
|
||||
cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (get_attr_length (insn) == 2)
|
||||
return \"b%k1 %l0\";
|
||||
else if (get_attr_length (insn) == 4)
|
||||
@ -1689,7 +1707,7 @@
|
||||
extu.l %S0
|
||||
mov.w %T1,%T0\;extu.l %S0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set_znv,set_znv")])
|
||||
|
||||
(define_expand "extendqihi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
@ -1715,7 +1733,7 @@
|
||||
exts.w %T0
|
||||
mov.b %R1,%s0\;exts.w %T0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set_znv,set_znv")])
|
||||
|
||||
;; The compiler can synthesize a 300H variant of this which is
|
||||
;; just as efficient as one that we'd create
|
||||
@ -1772,7 +1790,7 @@
|
||||
exts.l %S0
|
||||
mov.w %T1,%T0\;exts.l %S0"
|
||||
[(set_attr "length" "2,4")
|
||||
(set_attr "cc" "set_zn_c0,set_zn_c0")])
|
||||
(set_attr "cc" "set_znv,set_znv")])
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; SHIFTS
|
||||
@ -2242,7 +2260,7 @@
|
||||
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
|
||||
"mov.w @(%u4,%T1),%T0"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:HI (match_operand:HI 1 "register_operand" "r")
|
||||
@ -2254,7 +2272,7 @@
|
||||
"(INTVAL(operands[2]) == INTVAL(operands[4])+1) && REGNO(operands[0]) +1 == REGNO(operands[3])"
|
||||
"mov.w %T0,@(%u4,%T1)"
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
;; Notice a move which could be post incremented.
|
||||
|
||||
@ -2265,7 +2283,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.b @%T1+,%X0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:HI 0 "register_operand" "")
|
||||
@ -2274,7 +2292,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.w @%T1+,%T0"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
;; Notice a move which could be predecremented.
|
||||
|
||||
@ -2286,7 +2304,7 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.b %X0,@-%T1"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:HI 1 "register_operand" "")
|
||||
@ -2296,5 +2314,5 @@
|
||||
"REGNO(operands[1]) != REGNO(operands[0])"
|
||||
"mov.w %T0,@-%T1"
|
||||
[(set_attr "length" "2")
|
||||
(set_attr "cc" "set_zn_c0")])
|
||||
(set_attr "cc" "set_znv")])
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user