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ia64.md (addsi3): Remove expander.

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* config/ia64/ia64.md (addsi3): Remove expander.
        (subsi3, mulsi3, negsi2, one_cmplsi2): Likewise.
        (*addsi3_shladd): New.

From-SVN: r35649
This commit is contained in:
Richard Henderson 2000-08-11 16:48:26 -07:00 committed by Richard Henderson
parent 870f9ec0bc
commit 058557c4d1
2 changed files with 20 additions and 124 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2000-08-11 Richard Henderson <rth@cygnus.com>
* config/ia64/ia64.md (addsi3): Remove expander.
(subsi3, mulsi3, negsi2, one_cmplsi2): Likewise.
(*addsi3_shladd): New.
2000-08-11 Richard Henderson <rth@cygnus.com>
* config/ia64/ia64.c (do_spill): Pass cfa offset to move expander.

138
gcc/config/ia64/ia64.md
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@ -1087,33 +1087,7 @@
;; ::
;; ::::::::::::::::::::
;; We handle 32-bit arithmetic just like the alpha port does.
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "reg_or_22bit_operand" "")))]
""
"
{
if (optimize)
{
rtx op1 = gen_lowpart (DImode, operands[1]);
rtx op2 = gen_lowpart (DImode, operands[2]);
if (! cse_not_expected)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_adddi3 (tmp, op1, op2));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
}
else
emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
DONE;
}
}")
(define_insn "*addsi3_internal"
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%r,r,a")
(match_operand:SI 2 "reg_or_22bit_operand" "r,I,J")))]
@ -1142,31 +1116,16 @@
"add %0 = %1, %1, 1"
[(set_attr "type" "A")])
(define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "")
(minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "")
(match_operand:SI 2 "register_operand" "")))]
(define_insn "*addsi3_shladd"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "shladd_operand" "n"))
(match_operand:SI 3 "register_operand" "r")))]
""
"
{
if (optimize)
{
rtx op1 = gen_lowpart (DImode, operands[1]);
rtx op2 = gen_lowpart (DImode, operands[2]);
"shladd %0 = %1, %S2, %3"
[(set_attr "type" "A")])
if (! cse_not_expected)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_subdi3 (tmp, op1, op2));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
}
else
emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
DONE;
}
}")
(define_insn "*subsi3_internal"
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "rK")
(match_operand:SI 2 "register_operand" "r")))]
@ -1182,33 +1141,9 @@
"sub %0 = %2, %1, 1"
[(set_attr "type" "A")])
(define_expand "mulsi3"
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "register_operand" "")))]
""
"
{
if (optimize)
{
rtx op1 = gen_lowpart (DImode, operands[1]);
rtx op2 = gen_lowpart (DImode, operands[2]);
if (! cse_not_expected)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_muldi3 (tmp, op1, op2));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
}
else
emit_insn (gen_muldi3 (gen_lowpart (DImode, operands[0]), op1, op2));
DONE;
}
}")
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
(define_insn "*mulsi3_internal"
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=f")
(mult:SI (match_operand:SI 1 "register_operand" "f")
(match_operand:SI 2 "nonmemory_operand" "f")))]
@ -1216,29 +1151,7 @@
"xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
(define_expand "negsi2"
[(set (match_operand:SI 0 "register_operand" "")
(neg:SI (match_operand:SI 1 "register_operand" "")))]
""
"
{
if (optimize)
{
rtx op1 = gen_lowpart (DImode, operands[1]);
if (! cse_not_expected)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_negdi2 (tmp, op1));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
}
else
emit_insn (gen_negdi2 (gen_lowpart (DImode, operands[0]), op1));
DONE;
}
}")
(define_insn "*negsi2_internal"
(define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
@ -1970,7 +1883,7 @@
;; ::::::::::::::::::::
;; ::
;; :: 32 Bit Integer Logical operations
;; :: 32 bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
@ -1988,39 +1901,16 @@
;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
;; one_cmplsi2 pattern.
(define_expand "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "")
(not:SI (match_operand:SI 1 "register_operand" "")))]
""
"
{
if (optimize)
{
rtx op1 = gen_lowpart (DImode, operands[1]);
if (! cse_not_expected)
{
rtx tmp = gen_reg_rtx (DImode);
emit_insn (gen_one_cmpldi2 (tmp, op1));
emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
}
else
emit_insn (gen_one_cmpldi2 (gen_lowpart (DImode, operands[0]), op1));
DONE;
}
}")
(define_insn "*one_cmplsi2_internal"
(define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
"andcm %0 = -1, %1"
[(set_attr "type" "A")])
;; ::::::::::::::::::::
;; ::
;; :: 64 Bit Integer Logical operations
;; :: 64 bit Integer Logical operations
;; ::
;; ::::::::::::::::::::