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rs6000.c (rs6000_expand_unop_builtin): Check icode not CODE_FOR_nothing.

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2002-07-30  David Edelsohn  <edelsohn@gnu.org>
            Zack Weinberg  <zack@codesourcery.com>

        * rs6000.c (rs6000_expand_unop_builtin): Check icode not
        CODE_FOR_nothing.  Change switch to if.
        (rs6000_expand_binop_builtin): Same.
        (rs6000_expand_builtin): Expand builtin if target support enabled.
        (rs6000_init_builtins): Init builtin if target support enabled.
        (rs6000_common_init_builtins): Check icode not CODE_FOR_nothing.

Co-Authored-By: Zack Weinberg <zack@codesourcery.com>

From-SVN: r55882
This commit is contained in:
David Edelsohn 2002-07-30 21:23:46 +00:00 committed by David Edelsohn
parent 60b8aa9433
commit 0559cc7752
2 changed files with 69 additions and 55 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2002-07-30 David Edelsohn <edelsohn@gnu.org>
Zack Weinberg <zack@codesourcery.com>
* rs6000.c (rs6000_expand_unop_builtin): Check icode not
CODE_FOR_nothing. Change switch to if.
(rs6000_expand_binop_builtin): Same.
(rs6000_expand_builtin): Expand builtin if target support enabled.
(rs6000_init_builtins): Init builtin if target support enabled.
(rs6000_common_init_builtins): Check icode not CODE_FOR_nothing.
2002-07-30 Franz Sirl <Franz.Sirl-kernel@lauterbach.com>
* gcc.c (cpp_unique_options): Define __GXX_ABI_VERSION, bump it to 101.

114
gcc/config/rs6000/rs6000.c
View File

@ -4085,18 +4085,21 @@ rs6000_expand_unop_builtin (icode, arglist, target)
enum machine_mode tmode = insn_data[icode].operand[0].mode;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
if (icode == CODE_FOR_nothing)
/* Builtin not supported on this processor. */
return 0;
/* If we got invalid arguments bail out before generating bad rtl. */
if (arg0 == error_mark_node)
return const0_rtx;
switch (icode)
if (icode == CODE_FOR_altivec_vspltisb
|| icode == CODE_FOR_altivec_vspltish
|| icode == CODE_FOR_altivec_vspltisw
|| icode == CODE_FOR_spe_evsplatfi
|| icode == CODE_FOR_spe_evsplati)
{
/* Only allow 5-bit *signed* literals. */
case CODE_FOR_altivec_vspltisb:
case CODE_FOR_altivec_vspltish:
case CODE_FOR_altivec_vspltisw:
case CODE_FOR_spe_evsplatfi:
case CODE_FOR_spe_evsplati:
if (GET_CODE (op0) != CONST_INT
|| INTVAL (op0) > 0x1f
|| INTVAL (op0) < -0x1f)
@ -4104,9 +4107,6 @@ rs6000_expand_unop_builtin (icode, arglist, target)
error ("argument 1 must be a 5-bit signed literal");
return const0_rtx;
}
break;
default:
break;
}
if (target == 0
@ -4175,45 +4175,45 @@ rs6000_expand_binop_builtin (icode, arglist, target)
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
enum machine_mode mode1 = insn_data[icode].operand[2].mode;
if (icode == CODE_FOR_nothing)
/* Builtin not supported on this processor. */
return 0;
/* If we got invalid arguments bail out before generating bad rtl. */
if (arg0 == error_mark_node || arg1 == error_mark_node)
return const0_rtx;
switch (icode)
if (icode == CODE_FOR_altivec_vcfux
|| icode == CODE_FOR_altivec_vcfsx
|| icode == CODE_FOR_altivec_vctsxs
|| icode == CODE_FOR_altivec_vctuxs
|| icode == CODE_FOR_altivec_vspltb
|| icode == CODE_FOR_altivec_vsplth
|| icode == CODE_FOR_altivec_vspltw
|| icode == CODE_FOR_spe_evaddiw
|| icode == CODE_FOR_spe_evldd
|| icode == CODE_FOR_spe_evldh
|| icode == CODE_FOR_spe_evldw
|| icode == CODE_FOR_spe_evlhhesplat
|| icode == CODE_FOR_spe_evlhhossplat
|| icode == CODE_FOR_spe_evlhhousplat
|| icode == CODE_FOR_spe_evlwhe
|| icode == CODE_FOR_spe_evlwhos
|| icode == CODE_FOR_spe_evlwhou
|| icode == CODE_FOR_spe_evlwhsplat
|| icode == CODE_FOR_spe_evlwwsplat
|| icode == CODE_FOR_spe_evrlwi
|| icode == CODE_FOR_spe_evslwi
|| icode == CODE_FOR_spe_evsrwis
|| icode == CODE_FOR_spe_evsrwiu)
{
/* Only allow 5-bit unsigned literals. */
case CODE_FOR_altivec_vcfux:
case CODE_FOR_altivec_vcfsx:
case CODE_FOR_altivec_vctsxs:
case CODE_FOR_altivec_vctuxs:
case CODE_FOR_altivec_vspltb:
case CODE_FOR_altivec_vsplth:
case CODE_FOR_altivec_vspltw:
case CODE_FOR_spe_evaddiw:
case CODE_FOR_spe_evldd:
case CODE_FOR_spe_evldh:
case CODE_FOR_spe_evldw:
case CODE_FOR_spe_evlhhesplat:
case CODE_FOR_spe_evlhhossplat:
case CODE_FOR_spe_evlhhousplat:
case CODE_FOR_spe_evlwhe:
case CODE_FOR_spe_evlwhos:
case CODE_FOR_spe_evlwhou:
case CODE_FOR_spe_evlwhsplat:
case CODE_FOR_spe_evlwwsplat:
case CODE_FOR_spe_evrlwi:
case CODE_FOR_spe_evslwi:
case CODE_FOR_spe_evsrwis:
case CODE_FOR_spe_evsrwiu:
if (TREE_CODE (arg1) != INTEGER_CST
|| TREE_INT_CST_LOW (arg1) & ~0x1f)
{
error ("argument 2 must be a 5-bit unsigned literal");
return const0_rtx;
}
break;
default:
break;
}
if (target == 0
@ -5095,23 +5095,26 @@ rs6000_expand_builtin (exp, target, subtarget, mode, ignore)
return ret;
}
/* Handle simple unary operations. */
d = (struct builtin_description *) bdesc_1arg;
for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_unop_builtin (d->icode, arglist, target);
if (TARGET_ALTIVEC || TARGET_SPE)
{
/* Handle simple unary operations. */
d = (struct builtin_description *) bdesc_1arg;
for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_unop_builtin (d->icode, arglist, target);
/* Handle simple binary operations. */
d = (struct builtin_description *) bdesc_2arg;
for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_binop_builtin (d->icode, arglist, target);
/* Handle simple binary operations. */
d = (struct builtin_description *) bdesc_2arg;
for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_binop_builtin (d->icode, arglist, target);
/* Handle simple ternary operations. */
d = (struct builtin_description *) bdesc_3arg;
for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_ternop_builtin (d->icode, arglist, target);
/* Handle simple ternary operations. */
d = (struct builtin_description *) bdesc_3arg;
for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
if (d->code == fcode)
return rs6000_expand_ternop_builtin (d->icode, arglist, target);
}
abort ();
return NULL_RTX;
@ -5124,7 +5127,8 @@ rs6000_init_builtins ()
spe_init_builtins ();
if (TARGET_ALTIVEC)
altivec_init_builtins ();
rs6000_common_init_builtins ();
if (TARGET_ALTIVEC || TARGET_SPE)
rs6000_common_init_builtins ();
}
/* Search through a set of builtins and enable the mask bits.
@ -5738,7 +5742,7 @@ rs6000_common_init_builtins (void)
enum machine_mode mode0, mode1, mode2, mode3;
tree type;
if (d->name == 0)
if (d->name == 0 || d->icode == CODE_FOR_nothing)
continue;
mode0 = insn_data[d->icode].operand[0].mode;
@ -5830,7 +5834,7 @@ rs6000_common_init_builtins (void)
enum machine_mode mode0, mode1, mode2;
tree type;
if (d->name == 0)
if (d->name == 0 || d->icode == CODE_FOR_nothing)
continue;
mode0 = insn_data[d->icode].operand[0].mode;
@ -5966,7 +5970,7 @@ rs6000_common_init_builtins (void)
enum machine_mode mode0, mode1;
tree type;
if (d->name == 0)
if (d->name == 0 || d->icode == CODE_FOR_nothing)
continue;
mode0 = insn_data[d->icode].operand[0].mode;