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arm.md (andsi_not_shiftsi_si_scc): New pattern.
gcc/config 2015-05-18 Alex Velenko <Alex.Velenko@arm.com> * arm/arm.md (andsi_not_shiftsi_si_scc): New pattern. (andsi_not_shiftsi_si_scc_no_reuse): New pattern. gcc/testsuite 2015-05-18 Alex Velenko <Alex.Velenko@arm.com> * gcc.target/arm/bics_1.c : New testcase. * gcc.target/arm/bics_2.c : New testcase. * gcc.target/arm/bics_3.c : New testcase. * gcc.target/arm/bics_4.c : New testcase. From-SVN: r223295
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Alex Velenko
Alex Velenko
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@ -1,3 +1,8 @@
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2015-05-18 Alex Velenko <Alex.Velenko@arm.com>
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* config/arm/arm.md (andsi_not_shiftsi_si_scc): New pattern.
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(andsi_not_shiftsi_si_scc_no_reuse): New pattern.
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2015-05-18 Robert Suchanek <robert.suchanek@imgtec.com>
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* config/mips/mips.c (micromips_globals): New variable.
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@ -2783,6 +2783,55 @@
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(const_string "logic_shift_reg")))]
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)
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;; Shifted bics pattern used to set up CC status register and not reusing
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;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2
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;; does not support shift by register.
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(define_insn "andsi_not_shiftsi_si_scc_no_reuse"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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(and:SI (not:SI (match_operator:SI 0 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")]))
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(match_operand:SI 3 "s_register_operand" "r"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r"))]
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"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
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"bic%.%?\\t%4, %3, %1%S0"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "logic_shift_imm")
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(const_string "logic_shift_reg")))]
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)
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;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also
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;; getting reused later.
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(define_insn "andsi_not_shiftsi_si_scc"
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[(parallel [(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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(and:SI (not:SI (match_operator:SI 0 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")]))
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(match_operand:SI 3 "s_register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 4 "s_register_operand" "=r")
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(and:SI (not:SI (match_op_dup 0
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[(match_dup 1)
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(match_dup 2)]))
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(match_dup 3)))])]
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"TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))"
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"bic%.%?\\t%4, %3, %1%S0"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")
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(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "logic_shift_imm")
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(const_string "logic_shift_reg")))]
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)
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(define_insn "*andsi_notsi_si_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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@ -1,3 +1,10 @@
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2015-05-18 Alex Velenko <Alex.Velenko@arm.com>
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* gcc.target/arm/bics_1.c : New testcase.
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* gcc.target/arm/bics_2.c : New testcase.
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* gcc.target/arm/bics_3.c : New testcase.
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* gcc.target/arm/bics_4.c : New testcase.
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2015-05-18 Robert Suchanek <robert.suchanek@imgtec.com>
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* gcc.target/mips/umips-attr.c: New test.
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54
gcc/testsuite/gcc.target/arm/bics_1.c
Normal file
54
gcc/testsuite/gcc.target/arm/bics_1.c
Normal file
@ -0,0 +1,54 @@
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/* { dg-do run } */
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/* { dg-options "-O2 --save-temps -fno-inline" } */
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/* { dg-require-effective-target arm32 } */
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extern void abort (void);
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int
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bics_si_test1 (int a, int b, int c)
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{
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int d = a & ~b;
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/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */
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if (d == 0)
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return a + c;
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else
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return b + d + c;
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}
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int
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bics_si_test2 (int a, int b, int c)
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{
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int d = a & ~(b << 3);
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/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl \#3" 1 } } */
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if (d == 0)
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return a + c;
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else
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return b + d + c;
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}
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int
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main ()
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{
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int x;
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x = bics_si_test1 (29, ~4, 5);
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if (x != ((29 & 4) + ~4 + 5))
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abort ();
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x = bics_si_test1 (5, ~2, 20);
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if (x != 25)
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abort ();
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x = bics_si_test2 (35, ~4, 5);
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if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
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abort ();
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x = bics_si_test2 (96, ~2, 20);
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if (x != 116)
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abort ();
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return 0;
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}
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/* { dg-final { cleanup-saved-temps } } */
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57
gcc/testsuite/gcc.target/arm/bics_2.c
Normal file
57
gcc/testsuite/gcc.target/arm/bics_2.c
Normal file
@ -0,0 +1,57 @@
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/* { dg-do run } */
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/* { dg-options "-O2 --save-temps -fno-inline" } */
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/* { dg-require-effective-target arm32 } */
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extern void abort (void);
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int
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bics_si_test1 (int a, int b, int c)
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{
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int d = a & ~b;
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/* { dg-final { scan-assembler-not "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" } } */
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/* { dg-final { scan-assembler-times "bic\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */
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if (d <= 0)
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return a + c;
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else
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return b + d + c;
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}
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int
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bics_si_test2 (int a, int b, int c)
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{
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int d = a & ~(b << 3);
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/* { dg-final { scan-assembler-not "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl \#3" } } */
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/* { dg-final { scan-assembler "bic\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl \#3" } } */
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if (d <= 0)
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return a + c;
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else
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return b + d + c;
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}
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int
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main ()
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{
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int x;
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x = bics_si_test1 (29, ~4, 5);
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if (x != ((29 & 4) + ~4 + 5))
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abort ();
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x = bics_si_test1 (5, ~2, 20);
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if (x != 25)
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abort ();
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x = bics_si_test2 (35, ~4, 5);
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if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
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abort ();
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x = bics_si_test2 (96, ~2, 20);
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if (x != 116)
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abort ();
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return 0;
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}
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/* { dg-final { cleanup-saved-temps } } */
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41
gcc/testsuite/gcc.target/arm/bics_3.c
Normal file
41
gcc/testsuite/gcc.target/arm/bics_3.c
Normal file
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/* { dg-do run } */
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/* { dg-options "-O2 --save-temps -fno-inline" } */
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/* { dg-require-effective-target arm32 } */
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extern void abort (void);
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int
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bics_si_test (int a, int b)
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{
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if (a & ~b)
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return 1;
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else
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return 0;
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}
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int
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bics_si_test2 (int a, int b)
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{
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if (a & ~ (b << 2))
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return 1;
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else
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return 0;
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}
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int
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main (void)
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{
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int a = 5;
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int b = 5;
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int c = 20;
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if (bics_si_test (a, b))
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abort ();
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if (bics_si_test2 (c, b))
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abort ();
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return 0;
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}
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/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */
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/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+, .sl #2" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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49
gcc/testsuite/gcc.target/arm/bics_4.c
Normal file
49
gcc/testsuite/gcc.target/arm/bics_4.c
Normal file
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/* { dg-do run } */
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/* { dg-options "-O2 --save-temps -fno-inline" } */
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/* { dg-require-effective-target arm32 } */
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extern void abort (void);
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int
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bics_si_test1 (int a, int b, int c)
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{
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if ((a & b) == a)
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return a;
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else
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return c;
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}
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int
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bics_si_test2 (int a, int b, int c)
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{
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if ((a & b) == b)
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return b;
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else
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return c;
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}
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int
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main ()
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{
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int x;
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x = bics_si_test1 (0xf00d, 0xf11f, 0);
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if (x != 0xf00d)
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abort ();
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x = bics_si_test1 (0xf11f, 0xf00d, 0);
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if (x != 0)
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abort ();
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x = bics_si_test2 (0xf00d, 0xf11f, 0);
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if (x != 0)
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abort ();
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x = bics_si_test2 (0xf11f, 0xf00d, 0);
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if (x != 0xf00d)
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abort ();
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return 0;
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}
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/* { dg-final { scan-assembler-times "bics\tr\[0-9\]+, r\[0-9\]+, r\[0-9\]+" 2 } } */
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/* { dg-final { cleanup-saved-temps } } */
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