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re PR target/33479 (SyncTest Intermittent failing on MIPS)
2007-09-26 David Daney <ddaney@avtrex.com> PR target/33479 * config/mips/mips.md (sync_compare_and_swap<mode>, sync_old_add<mode>, sync_new_add<mode>, sync_old_<optab><mode>, sync_new_<optab><mode>, sync_old_nand<mode>, sync_new_nand<mode>, sync_lock_test_and_set<mode>): Fix '&' constraint modifiers. Update length attributes. (sync_add<mode>, sync_sub<mode>, sync_old_sub<mode>, sync_new_sub<mode>, sync_<optab><mode>, sync_nand<mode>): Update length attributes. * config/mips/mips.h (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP, MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Add post-loop sync. From-SVN: r128821
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David Daney
David Daney
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e2e79a188a
commit
01fdb4cf5d
@ -1,3 +1,19 @@
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2007-09-26 David Daney <ddaney@avtrex.com>
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PR target/33479
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* config/mips/mips.md (sync_compare_and_swap<mode>, sync_old_add<mode>,
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sync_new_add<mode>, sync_old_<optab><mode>, sync_new_<optab><mode>,
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sync_old_nand<mode>, sync_new_nand<mode>,
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sync_lock_test_and_set<mode>): Fix '&' constraint modifiers.
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Update length attributes.
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(sync_add<mode>, sync_sub<mode>, sync_old_sub<mode>,
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sync_new_sub<mode>, sync_<optab><mode>, sync_nand<mode>): Update
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length attributes.
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* config/mips/mips.h (MIPS_COMPARE_AND_SWAP, MIPS_SYNC_OP,
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MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP, MIPS_SYNC_NAND,
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MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND, MIPS_SYNC_EXCHANGE): Add
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post-loop sync.
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2007-09-26 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/33563
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@ -2952,11 +2952,10 @@ while (0)
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\tbne\t%0,%2,2f\n" \
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"\t" OP "\t%@,%3\n" \
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"\tsc" SUFFIX "\t%@,%1" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop\n" \
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"2:%]%>%)"
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"2:\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -2968,10 +2967,10 @@ while (0)
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%@,%0\n" \
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"\t" INSN "\t%@,%@,%1\n" \
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"\tsc" SUFFIX "\t%@,%0" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%0\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop%]%>%)"
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"\tnop\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -2985,10 +2984,10 @@ while (0)
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tsc" SUFFIX "\t%@,%1" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop%]%>%)"
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"\tnop\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3002,10 +3001,10 @@ while (0)
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tsc" SUFFIX "\t%@,%1" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\t" INSN "\t%0,%0,%2%]%>%)"
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"\t" INSN "\t%0,%0,%2\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3019,10 +3018,10 @@ while (0)
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"1:\tll" SUFFIX "\t%@,%0\n" \
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"\tnor\t%@,%@,%.\n" \
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"\t" INSN "\t%@,%@,%1\n" \
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"\tsc" SUFFIX "\t%@,%0" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%0\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop%]%>%)"
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"\tnop\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3038,10 +3037,10 @@ while (0)
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\tnor\t%@,%0,%.\n" \
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"\t" INSN "\t%@,%@,%2\n" \
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"\tsc" SUFFIX "\t%@,%1" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\tnop%]%>%)"
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"\tnop\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -3057,10 +3056,10 @@ while (0)
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\tnor\t%0,%0,%.\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tsc" SUFFIX "\t%@,%1" \
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"%-\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq\t%@,%.,1b\n" \
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"\t" INSN "\t%0,%0,%2%]%>%)"
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"\t" INSN "\t%0,%0,%2\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -4328,7 +4328,7 @@
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"%|sync%-")
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(define_insn "sync_compare_and_swap<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
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@ -4341,7 +4341,7 @@
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else
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return MIPS_COMPARE_AND_SWAP ("<d>", "move");
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}
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[(set_attr "length" "28")])
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[(set_attr "length" "32")])
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(define_insn "sync_add<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+R,R")
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@ -4356,7 +4356,7 @@
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else
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return MIPS_SYNC_OP ("<d>", "<d>addu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_sub<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+R")
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@ -4366,12 +4366,12 @@
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UNSPEC_SYNC_OLD_OP))]
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"GENERATE_LL_SC"
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{
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return MIPS_SYNC_OP ("<d>", "<d>subu");
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return MIPS_SYNC_OP ("<d>", "<d>subu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_old_add<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR
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@ -4385,7 +4385,7 @@
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else
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return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_old_sub<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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@ -4399,10 +4399,10 @@
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{
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return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_new_add<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
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(match_operand:GPR 2 "arith_operand" "I,d")))
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(set (match_dup 1)
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@ -4416,7 +4416,7 @@
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else
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return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_new_sub<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d")
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@ -4430,7 +4430,7 @@
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{
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return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_<optab><mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+R,R")
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@ -4445,10 +4445,10 @@
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else
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return MIPS_SYNC_OP ("<d>", "<insn>");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_old_<optab><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR
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@ -4462,10 +4462,10 @@
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else
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return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_new_<optab><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR
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@ -4479,7 +4479,7 @@
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else
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return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
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}
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[(set_attr "length" "24")])
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[(set_attr "length" "28")])
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(define_insn "sync_nand<mode>"
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[(set (match_operand:GPR 0 "memory_operand" "+R,R")
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@ -4492,10 +4492,10 @@
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else
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return MIPS_SYNC_NAND ("<d>", "and");
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}
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[(set_attr "length" "28")])
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[(set_attr "length" "32")])
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(define_insn "sync_old_nand<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
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@ -4507,10 +4507,10 @@
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else
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return MIPS_SYNC_OLD_NAND ("<d>", "and");
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}
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[(set_attr "length" "28")])
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[(set_attr "length" "32")])
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(define_insn "sync_new_nand<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
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@ -4522,10 +4522,10 @@
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else
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return MIPS_SYNC_NEW_NAND ("<d>", "and");
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}
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[(set_attr "length" "28")])
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[(set_attr "length" "32")])
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(define_insn "sync_lock_test_and_set<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=&d,d")
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[(set (match_operand:GPR 0 "register_operand" "=d,&d")
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(match_operand:GPR 1 "memory_operand" "+R,R"))
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(set (match_dup 1)
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(unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
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