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arm: Improve thumb1_gen_const_int
Enable thumb1_gen_const_int to generate RTL or asm depending on the
context, so that we avoid duplicating code to handle constants in
Thumb-1 with -mpure-code.
Use a template so that the algorithm is effectively shared, and
rely on two classes to handle the actual emission as RTL or asm.
The generated sequence is improved to handle right-shiftable and small
values with less instructions. We now generate:
128:
movs r0, r0, #128
264:
movs r3, #33
lsls r3, #3
510:
movs r3, #255
lsls r3, #1
512:
movs r3, #1
lsls r3, #9
764:
movs r3, #191
lsls r3, #2
65536:
movs r3, #1
lsls r3, #16
0x123456:
movs r3, #18 ;0x12
lsls r3, #8
adds r3, #52 ;0x34
lsls r3, #8
adds r3, #86 ;0x56
0x1123456:
movs r3, #137 ;0x89
lsls r3, #8
adds r3, #26 ;0x1a
lsls r3, #8
adds r3, #43 ;0x2b
lsls r3, #1
0x1000010:
movs r3, #16
lsls r3, #16
adds r3, #1
lsls r3, #4
0x1000011:
movs r3, #1
lsls r3, #24
adds r3, #17
-8192:
movs r3, #1
lsls r3, #13
rsbs r3, #0
The patch adds a testcase which does not fully exercise
thumb1_gen_const_int, as other existing patterns already catch small
constants. These parts of thumb1_gen_const_int are used by
arm_thumb1_mi_thunk.
2020-11-02 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* config/arm/arm.c (thumb1_const_rtl, thumb1_const_print): New
classes.
(thumb1_gen_const_int): Rename to ...
(thumb1_gen_const_int_1): ... New helper function. Add capability
to emit either RTL or asm, improve generated code.
(thumb1_gen_const_int_rtl): New function.
* config/arm/arm-protos.h (thumb1_gen_const_int): Rename to
thumb1_gen_const_int_rtl.
* config/arm/thumb1.md: Call thumb1_gen_const_int_rtl instead
of thumb1_gen_const_int.
gcc/testsuite/
* gcc.target/arm/pure-code/no-literal-pool-m0.c: New.
This commit is contained in:
Christophe Lyon
parent
79680c1d5c
commit
011f5e92f8
@ -74,7 +74,7 @@ extern bool arm_small_register_classes_for_mode_p (machine_mode);
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extern int const_ok_for_arm (HOST_WIDE_INT);
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extern int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
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extern int const_ok_for_dimode_op (HOST_WIDE_INT, enum rtx_code);
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extern void thumb1_gen_const_int (rtx, HOST_WIDE_INT);
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extern void thumb1_gen_const_int_rtl (rtx, HOST_WIDE_INT);
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extern int arm_split_constant (RTX_CODE, machine_mode, rtx,
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HOST_WIDE_INT, rtx, rtx, int);
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extern int legitimate_pic_operand_p (rtx);
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@ -4528,38 +4528,6 @@ const_ok_for_dimode_op (HOST_WIDE_INT i, enum rtx_code code)
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}
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}
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/* Emit a sequence of movs/adds/shift to produce a 32-bit constant.
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Avoid generating useless code when one of the bytes is zero. */
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void
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thumb1_gen_const_int (rtx op0, HOST_WIDE_INT op1)
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{
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bool mov_done_p = false;
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int i;
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/* Emit upper 3 bytes if needed. */
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for (i = 0; i < 3; i++)
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{
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int byte = (op1 >> (8 * (3 - i))) & 0xff;
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if (byte)
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{
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emit_set_insn (op0, mov_done_p
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? gen_rtx_PLUS (SImode,op0, GEN_INT (byte))
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: GEN_INT (byte));
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mov_done_p = true;
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}
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if (mov_done_p)
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emit_set_insn (op0, gen_rtx_ASHIFT (SImode, op0, GEN_INT (8)));
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}
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/* Emit lower byte if needed. */
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if (!mov_done_p)
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emit_set_insn (op0, GEN_INT (op1 & 0xff));
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else if (op1 & 0xff)
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emit_set_insn (op0, gen_rtx_PLUS (SImode, op0, GEN_INT (op1 & 0xff)));
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}
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/* Emit a sequence of insns to handle a large constant.
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CODE is the code of the operation required, it can be any of SET, PLUS,
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IOR, AND, XOR, MINUS;
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@ -28263,6 +28231,198 @@ arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
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default_internal_label (stream, prefix, labelno);
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}
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/* Define classes to generate code as RTL or output asm to a file.
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Using templates then allows to use the same code to output code
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sequences in the two formats. */
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class thumb1_const_rtl
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{
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public:
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thumb1_const_rtl (rtx dst) : dst (dst) {}
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void mov (HOST_WIDE_INT val)
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{
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emit_set_insn (dst, GEN_INT (val));
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}
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void add (HOST_WIDE_INT val)
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{
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emit_set_insn (dst, gen_rtx_PLUS (SImode, dst, GEN_INT (val)));
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}
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void ashift (HOST_WIDE_INT shift)
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{
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emit_set_insn (dst, gen_rtx_ASHIFT (SImode, dst, GEN_INT (shift)));
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}
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void neg ()
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{
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emit_set_insn (dst, gen_rtx_NEG (SImode, dst));
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}
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private:
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rtx dst;
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};
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class thumb1_const_print
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{
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public:
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thumb1_const_print (FILE *f, int regno)
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{
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t_file = f;
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dst_regname = reg_names[regno];
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}
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void mov (HOST_WIDE_INT val)
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{
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asm_fprintf (t_file, "\tmovs\t%s, #" HOST_WIDE_INT_PRINT_DEC "\n",
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dst_regname, val);
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}
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void add (HOST_WIDE_INT val)
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{
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asm_fprintf (t_file, "\tadds\t%s, #" HOST_WIDE_INT_PRINT_DEC "\n",
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dst_regname, val);
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}
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void ashift (HOST_WIDE_INT shift)
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{
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asm_fprintf (t_file, "\tlsls\t%s, #" HOST_WIDE_INT_PRINT_DEC "\n",
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dst_regname, shift);
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}
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void neg ()
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{
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asm_fprintf (t_file, "\trsbs\t%s, #0\n", dst_regname);
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}
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private:
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FILE *t_file;
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const char *dst_regname;
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};
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/* Emit a sequence of movs/adds/shift to produce a 32-bit constant.
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Avoid generating useless code when one of the bytes is zero. */
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template <class T>
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void
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thumb1_gen_const_int_1 (T dst, HOST_WIDE_INT op1)
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{
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bool mov_done_p = false;
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unsigned HOST_WIDE_INT val = op1;
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int shift = 0;
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int i;
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gcc_assert (op1 == trunc_int_for_mode (op1, SImode));
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if (val <= 255)
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{
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dst.mov (val);
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return;
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}
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/* For negative numbers with the first nine bits set, build the
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opposite of OP1, then negate it, it's generally shorter and not
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longer. */
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if ((val & 0xFF800000) == 0xFF800000)
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{
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thumb1_gen_const_int_1 (dst, -op1);
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dst.neg ();
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return;
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}
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/* In the general case, we need 7 instructions to build
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a 32 bits constant (1 movs, 3 lsls, 3 adds). We can
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do better if VAL is small enough, or
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right-shiftable by a suitable amount. If the
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right-shift enables to encode at least one less byte,
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it's worth it: we save a adds and a lsls at the
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expense of a final lsls. */
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int final_shift = number_of_first_bit_set (val);
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int leading_zeroes = clz_hwi (val);
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int number_of_bytes_needed
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= ((HOST_BITS_PER_WIDE_INT - 1 - leading_zeroes)
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/ BITS_PER_UNIT) + 1;
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int number_of_bytes_needed2
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= ((HOST_BITS_PER_WIDE_INT - 1 - leading_zeroes - final_shift)
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/ BITS_PER_UNIT) + 1;
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if (number_of_bytes_needed2 < number_of_bytes_needed)
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val >>= final_shift;
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else
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final_shift = 0;
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/* If we are in a very small range, we can use either a single movs
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or movs+adds. */
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if (val <= 510)
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{
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if (val > 255)
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{
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unsigned HOST_WIDE_INT high = val - 255;
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dst.mov (high);
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dst.add (255);
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}
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else
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dst.mov (val);
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if (final_shift > 0)
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dst.ashift (final_shift);
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}
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else
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{
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/* General case, emit upper 3 bytes as needed. */
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for (i = 0; i < 3; i++)
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{
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unsigned HOST_WIDE_INT byte = (val >> (8 * (3 - i))) & 0xff;
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if (byte)
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{
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/* We are about to emit new bits, stop accumulating a
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shift amount, and left-shift only if we have already
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emitted some upper bits. */
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if (mov_done_p)
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{
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dst.ashift (shift);
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dst.add (byte);
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}
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else
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dst.mov (byte);
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/* Stop accumulating shift amount since we've just
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emitted some bits. */
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shift = 0;
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mov_done_p = true;
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}
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if (mov_done_p)
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shift += 8;
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}
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/* Emit lower byte. */
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if (!mov_done_p)
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dst.mov (val & 0xff);
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else
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{
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dst.ashift (shift);
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if (val & 0xff)
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dst.add (val & 0xff);
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}
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if (final_shift > 0)
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dst.ashift (final_shift);
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}
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}
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/* Proxy for thumb1.md, since the thumb1_const_print and
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thumb1_const_rtl classes are not exported. */
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void
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thumb1_gen_const_int_rtl (rtx dst, HOST_WIDE_INT op1)
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{
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thumb1_const_rtl t (dst);
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thumb1_gen_const_int_1 (t, op1);
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}
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/* Output code to add DELTA to the first argument, and then jump
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to FUNCTION. Used for C++ multiple inheritance. */
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@ -820,7 +820,7 @@
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&& !satisfies_constraint_K (operands[1])"
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[(clobber (const_int 0))]
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"
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thumb1_gen_const_int (operands[0], INTVAL (operands[1]));
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thumb1_gen_const_int_rtl (operands[0], INTVAL (operands[1]));
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DONE;
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"
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)
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175
gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool-m0.c
Normal file
175
gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool-m0.c
Normal file
@ -0,0 +1,175 @@
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/* { dg-do compile } */
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/* { dg-options "-mpure-code -mcpu=cortex-m0 -march=armv6s-m -mthumb" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/* Does not use thumb1_gen_const_int.
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** test_0:
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** ...
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** movs r[0-3], #0
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** ...
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*/
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int
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test_0 ()
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{
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return 0;
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}
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/* Does not use thumb1_gen_const_int.
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** test_128:
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** ...
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** movs r[0-3], #128
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** ...
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*/
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int
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test_128 ()
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{
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return 128;
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}
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/* Does not use thumb1_gen_const_int.
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** test_264:
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** ...
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** movs r[0-3], #132
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** lsls r[0-3], r[0-3], #1
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** ...
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*/
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int
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test_264 ()
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{
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return 264;
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}
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/* Does not use thumb1_gen_const_int.
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** test_510:
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** ...
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** movs r[0-3], #255
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** lsls r[0-3], r[0-3], #1
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** ...
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*/
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int
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test_510 ()
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{
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return 510;
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}
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/* Does not use thumb1_gen_const_int.
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** test_512:
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** ...
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** movs r[0-3], #128
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** lsls r[0-3], r[0-3], #2
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** ...
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*/
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int
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test_512 ()
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{
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return 512;
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}
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/* Does not use thumb1_gen_const_int.
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** test_764:
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** ...
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** movs r[0-3], #191
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** lsls r[0-3], r[0-3], #2
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** ...
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*/
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int
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test_764 ()
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{
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return 764;
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}
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/* Does not use thumb1_gen_const_int.
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** test_65536:
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** ...
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** movs r[0-3], #128
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** lsls r[0-3], r[0-3], #9
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** ...
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*/
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int
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test_65536 ()
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{
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return 65536;
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}
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/*
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** test_0x123456:
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** ...
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** movs r[0-3], #18
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** lsls r[0-3], r[0-3], #8
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** adds r[0-3], r[0-3], #52
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** lsls r[0-3], r[0-3], #8
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** adds r[0-3], r[0-3], #86
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** ...
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*/
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int
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test_0x123456 ()
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{
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return 0x123456;
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}
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/*
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** test_0x1123456:
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** ...
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** movs r[0-3], #137
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** lsls r[0-3], r[0-3], #8
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** adds r[0-3], r[0-3], #26
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** lsls r[0-3], r[0-3], #8
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** adds r[0-3], r[0-3], #43
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** lsls r[0-3], r[0-3], #1
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** ...
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*/
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int
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test_0x1123456 ()
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{
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return 0x1123456;
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}
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/* With -Os, we generate:
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movs r0, #16
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lsls r0, r0, r0
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With the other optimization levels, we generate:
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movs r0, #16
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lsls r0, r0, #16
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hence the two alternatives. */
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/*
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** test_0x1000010:
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** ...
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** movs r[0-3], #16
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** lsls r[0-3], r[0-3], (#16|r[0-3])
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** adds r[0-3], r[0-3], #1
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** lsls r[0-3], r[0-3], #4
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** ...
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*/
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int
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test_0x1000010 ()
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{
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return 0x1000010;
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}
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/*
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** test_0x1000011:
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** ...
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** movs r[0-3], #1
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** lsls r[0-3], r[0-3], #24
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** adds r[0-3], r[0-3], #17
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** ...
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*/
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int
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test_0x1000011 ()
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{
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return 0x1000011;
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}
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/*
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** test_m8192:
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** ...
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** movs r[0-3], #1
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** lsls r[0-3], r[0-3], #13
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** rsbs r[0-3], r[0-3], #0
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** ...
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*/
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int
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test_m8192 ()
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{
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return -8192;
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}
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