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re PR middle-end/35854 (life passes dump option still documented)
2009-01-29 Kenneth Zadeck <zadeck@naturalbridge.com> PR middle-end/35854 * doc/invoke.texi (rtl debug options): Complete rewrite. * auto-inc-dec.c (pass_inc_dec): Rename pass from "auto-inc-dec" to auto_inc_dec". * mode-switching.c (pass_mode_switching): Rename pass from "mode-sw" to "mode_sw". * except.c (pass_convert_to_eh_ranges): Rename pass from "eh-ranges" to "eh_ranges". * lower-subreg.c (pass_lower_subreg): Renamed pass from "subreg" to "subreg1". 2009-01-29 Kenneth Zadeck <zadeck@naturalbridge.com> PR middle-end/35854 * gcc.dg/lower-subreg-1.c: Renamed dump pass from "subreg" to "subreg1" From-SVN: r143756
This commit is contained in:
Kenneth Zadeck
Kenneth Zadeck
parent
72a54528db
commit
00b251a037
@ -1,3 +1,17 @@
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2009-01-29 Kenneth Zadeck <zadeck@naturalbridge.com>
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PR middle-end/35854
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* doc/invoke.texi (rtl debug options): Complete rewrite.
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* auto-inc-dec.c (pass_inc_dec): Rename pass from "auto-inc-dec"
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to auto_inc_dec".
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* mode-switching.c (pass_mode_switching): Rename pass from
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"mode-sw" to "mode_sw".
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* except.c (pass_convert_to_eh_ranges): Rename pass from
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"eh-ranges" to "eh_ranges".
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* lower-subreg.c (pass_lower_subreg): Renamed pass from "subreg"
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to "subreg1".
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2009-01-29 Andrey Belevantsev <abel@ispras.ru>
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Alexander Monakov <amonakov@ispras.ru>
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@ -1544,7 +1544,7 @@ struct rtl_opt_pass pass_inc_dec =
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{
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{
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RTL_PASS,
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"auto-inc-dec", /* name */
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"auto_inc_dec", /* name */
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gate_auto_inc_dec, /* gate */
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rest_of_handle_auto_inc_dec, /* execute */
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NULL, /* sub */
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@ -4545,172 +4545,275 @@ preprocessing.
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Debug dumps can be enabled with a @option{-fdump-rtl} switch or some
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@option{-d} option @var{letters}. Here are the possible
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letters for use in @var{letters} and @var{pass}, and their meanings:
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letters for use in @var{pass} and @var{letters}, and their meanings:
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@table @gcctabopt
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@item -dA
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@opindex dA
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Annotate the assembler output with miscellaneous debugging information.
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@item -fdump-rtl-alignments
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@opindex fdump-rtl-alignments
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Dump after branch alignments have been computed.
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@item -fdump-rtl-asmcons
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@opindex fdump-rtl-asmcons
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Dump after fixing rtl statements that have unsatisfied in/out constraints.
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@item -fdump-rtl-auto_inc_dec
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@opindex fdump-rtl-auto_inc_dec
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Dump after auto-inc-dec discovery. This pass is only run on
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architectures that have auto inc or auto dec instructions.
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@item -fdump-rtl-barriers
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@opindex fdump-rtl-barriers
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Dump after cleaning up the barrier instructions.
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@item -fdump-rtl-bbpart
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@opindex fdump-rtl-bbpart
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Dump after partitioning hot and cold basic blocks.
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@item -fdump-rtl-bbro
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@opindex fdump-rtl-bbro
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Dump after block reordering, to @file{@var{file}.148r.bbro}.
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Dump after block reordering.
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@item -fdump-rtl-btl1
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@itemx -fdump-rtl-btl2
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@opindex fdump-rtl-btl2
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@opindex fdump-rtl-btl2
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@option{-fdump-rtl-btl1} and @option{-fdump-rtl-btl2} enable dumping
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after the two branch
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target load optimization passes.
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@item -fdump-rtl-bypass
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@opindex fdump-rtl-bypass
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Dump after jump bypassing and control flow optimizations.
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@item -fdump-rtl-combine
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@opindex fdump-rtl-combine
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Dump after the RTL instruction combination pass, to the file
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@file{@var{file}.129r.combine}.
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Dump after the RTL instruction combination pass.
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@item -fdump-rtl-compgotos
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@opindex fdump-rtl-compgotos
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Dump after dumplicating the computed gotos.
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@item -fdump-rtl-ce1
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@itemx -fdump-rtl-ce2
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@itemx -fdump-rtl-ce3
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@opindex fdump-rtl-ce1
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@opindex fdump-rtl-ce2
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@option{-fdump-rtl-ce1} enable dumping after the
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first if conversion, to the file @file{@var{file}.117r.ce1}.
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@option{-fdump-rtl-ce2} enable dumping after the second if
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conversion, to the file @file{@var{file}.130r.ce2}.
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@opindex fdump-rtl-ce3
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@option{-fdump-rtl-ce1}, @option{-fdump-rtl-ce2}, and
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@option{-fdump-rtl-ce3} enable dumping after the three
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if conversion passes.
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@itemx -fdump-rtl-cprop_hardreg
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@opindex fdump-rtl-cprop_hardreg
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Dump after hard register copy propagation.
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@itemx -fdump-rtl-csa
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@opindex fdump-rtl-csa
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Dump after combining stack adjustments.
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@item -fdump-rtl-cse1
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@itemx -fdump-rtl-cse2
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@opindex fdump-rtl-cse1
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@opindex fdump-rtl-cse2
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@option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
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the two common sub-expression elimination passes.
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@itemx -fdump-rtl-dce
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@opindex fdump-rtl-dce
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Dump after the standalone dead code elimination passes.
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@item -fdump-rtl-btl
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@itemx -fdump-rtl-dbr
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@opindex fdump-rtl-btl
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@opindex fdump-rtl-dbr
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@option{-fdump-rtl-btl} enable dumping after branch
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target load optimization, to @file{@var{file}.31.btl}.
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@option{-fdump-rtl-dbr} enable dumping after delayed branch
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scheduling, to @file{@var{file}.36.dbr}.
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Dump after delayed branch scheduling.
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@item -fdump-rtl-dce1
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@itemx -fdump-rtl-dce2
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@opindex fdump-rtl-dce1
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@opindex fdump-rtl-dce2
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@option{-fdump-rtl-dce1} and @option{-fdump-rtl-dce2} enable dumping after
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the two dead store elimination passes.
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@item -fdump-rtl-eh
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@opindex fdump-rtl-eh
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Dump after finalization of EH handling code.
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@item -fdump-rtl-eh_ranges
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@opindex fdump-rtl-eh_ranges
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Dump after conversion of EH handling range regions.
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@item -fdump-rtl-expand
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@opindex fdump-rtl-expand
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Dump after RTL generation.
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@item -fdump-rtl-fwprop1
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@itemx -fdump-rtl-fwprop2
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@opindex fdump-rtl-fwprop1
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@opindex fdump-rtl-fwprop2
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@option{-fdump-rtl-fwprop1} and @option{-fdump-rtl-fwprop2} enable
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dumping after the two forward propagation passes.
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@item -fdump-rtl-gcse1
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@itemx -fdump-rtl-gcse2
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@opindex fdump-rtl-gcse1
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@opindex fdump-rtl-gcse2
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@option{-fdump-rtl-gcse1} and @option{-fdump-rtl-gcse2} enable dumping
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after global common subexpression elimination.
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@item -fdump-rtl-init-regs
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@opindex fdump-rtl-init-regs
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Dump after the initialization of the registers.
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@item -fdump-rtl-initvals
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@opindex fdump-rtl-initvals
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Dump after the computation of the initial value sets.
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@itemx -fdump-rtl-into_cfglayout
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@opindex fdump-rtl-into_cfglayout
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Dump after converting to cfglayout mode.
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@item -fdump-rtl-ira
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@opindex fdump-rtl-ira
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Dump after iterated register allocation.
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@item -fdump-rtl-jump
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@opindex fdump-rtl-jump
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Dump after the second jump optimization.
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@item -fdump-rtl-loop2
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@opindex fdump-rtl-loop2
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@option{-fdump-rtl-loop2} enables dumping after the rtl
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loop optimization passes.
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@item -fdump-rtl-mach
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@opindex fdump-rtl-mach
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Dump after performing the machine dependent reorganization pass, if that
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pass exists.
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@item -fdump-rtl-mode_sw
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@opindex fdump-rtl-mode_sw
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Dump after removing redundant mode switches.
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@item -fdump-rtl-rnreg
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@opindex fdump-rtl-rnreg
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Dump after register renumbering.
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@itemx -fdump-rtl-outof_cfglayout
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@opindex fdump-rtl-outof_cfglayout
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Dump after converting from cfglayout mode.
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@item -fdump-rtl-peephole2
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@opindex fdump-rtl-peephole2
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Dump after the peephole pass.
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@item -fdump-rtl-postreload
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@opindex fdump-rtl-postreload
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Dump after post-reload optimizations.
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@itemx -fdump-rtl-pro_and_epilogue
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@opindex fdump-rtl-pro_and_epilogue
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Dump after generating the function pro and epilogues.
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@item -fdump-rtl-regmove
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@opindex fdump-rtl-regmove
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Dump after the register move pass.
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@item -fdump-rtl-sched1
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@itemx -fdump-rtl-sched2
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@opindex fdump-rtl-sched1
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@opindex fdump-rtl-sched2
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@option{-fdump-rtl-sched1} and @option{-fdump-rtl-sched2} enable dumping
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after the basic block scheduling passes.
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@item -fdump-rtl-see
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@opindex fdump-rtl-see
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Dump after sign extension elimination.
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@item -fdump-rtl-seqabstr
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@opindex fdump-rtl-seqabstr
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Dump after common sequence discovery.
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@item -fdump-rtl-shorten
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@opindex fdump-rtl-shorten
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Dump after shortening branches.
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@item -fdump-rtl-sibling
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@opindex fdump-rtl-sibling
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Dump after sibling call optimizations.
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@item -fdump-rtl-split1
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@itemx -fdump-rtl-split2
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@itemx -fdump-rtl-split3
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@itemx -fdump-rtl-split4
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@itemx -fdump-rtl-split5
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@opindex fdump-rtl-split1
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@opindex fdump-rtl-split2
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@opindex fdump-rtl-split3
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@opindex fdump-rtl-split4
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@opindex fdump-rtl-split5
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@option{-fdump-rtl-split1}, @option{-fdump-rtl-split2},
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@option{-fdump-rtl-split3}, @option{-fdump-rtl-split4} and
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@option{-fdump-rtl-split5} enable dumping after five rounds of
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instruction splitting.
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@item -fdump-rtl-sms
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@opindex fdump-rtl-sms
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Dump after modulo scheduling. This pass is only run on some
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architectures.
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@item -fdump-rtl-stack
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@opindex fdump-rtl-stack
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Dump after conversion from GCC's "flat register file" registers to the
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x87's stack-like registers. This pass is only run on x86 variants.
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@item -fdump-rtl-subreg1
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@itemx -fdump-rtl-subreg2
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@opindex fdump-rtl-subreg1
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@opindex fdump-rtl-subreg2
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@option{-fdump-rtl-subreg1} and @option{-fdump-rtl-subreg2} enable dumping after
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the two subreg expansion passes.
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@item -fdump-rtl-unshare
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@opindex fdump-rtl-unshare
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Dump after all rtl has been unshared.
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@item -fdump-rtl-vartrack
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@opindex fdump-rtl-vartrack
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Dump after variable tracking.
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@item -fdump-rtl-vregs
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@opindex fdump-rtl-vregs
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Dump after converting virtual registers to hard registers.
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@item -fdump-rtl-web
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@opindex fdump-rtl-web
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Dump after live range splitting.
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@item -fdump-rtl-regclass
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@itemx -fdump-rtl-subregs_of_mode_init
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@itemx -fdump-rtl-subregs_of_mode_finish
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@itemx -fdump-rtl-dfinit
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@itemx -fdump-rtl-dfinish
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@opindex fdump-rtl-regclass
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@opindex fdump-rtl-subregs_of_mode_init
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@opindex fdump-rtl-subregs_of_mode_finish
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@opindex fdump-rtl-dfinit
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@opindex fdump-rtl-dfinish
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These dumps are defined but always produce empty files.
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@item -fdump-rtl-all
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@opindex fdump-rtl-all
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Produce all the dumps listed above.
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@item -dA
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@opindex dA
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Annotate the assembler output with miscellaneous debugging information.
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@item -dD
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@opindex dD
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Dump all macro definitions, at the end of preprocessing, in addition to
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normal output.
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@item -fdump-rtl-ce3
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@opindex fdump-rtl-ce3
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Dump after the third if conversion, to @file{@var{file}.146r.ce3}.
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@item -fdump-rtl-cfg
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@itemx -fdump-rtl-life
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@opindex fdump-rtl-cfg
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@opindex fdump-rtl-life
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@option{-fdump-rtl-cfg} enable dumping after control
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and data flow analysis, to @file{@var{file}.116r.cfg}.
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@option{-fdump-rtl-cfg} enable dumping dump after life analysis,
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to @file{@var{file}.128r.life1} and @file{@var{file}.135r.life2}.
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@item -fdump-rtl-greg
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@opindex fdump-rtl-greg
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Dump after global register allocation, to @file{@var{file}.139r.greg}.
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@item -fdump-rtl-gcse
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@itemx -fdump-rtl-bypass
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@opindex fdump-rtl-gcse
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@opindex fdump-rtl-bypass
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@option{-fdump-rtl-gcse} enable dumping after GCSE, to
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@file{@var{file}.114r.gcse}. @option{-fdump-rtl-bypass}
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enable dumping after jump bypassing and control flow optimizations, to
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@file{@var{file}.115r.bypass}.
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@item -fdump-rtl-eh
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@opindex fdump-rtl-eh
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Dump after finalization of EH handling code, to @file{@var{file}.02.eh}.
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@item -fdump-rtl-sibling
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@opindex fdump-rtl-sibling
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Dump after sibling call optimizations, to @file{@var{file}.106r.sibling}.
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@item -fdump-rtl-jump
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@opindex fdump-rtl-jump
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Dump after the first jump optimization, to @file{@var{file}.112r.jump}.
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@item -fdump-rtl-stack
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@opindex fdump-rtl-stack
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Dump after conversion from GCC's "flat register file" registers to the
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x87's stack-like registers, to @file{@var{file}.152r.stack}.
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@item -fdump-rtl-lreg
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@opindex fdump-rtl-lreg
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Dump after local register allocation, to @file{@var{file}.138r.lreg}.
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@item -fdump-rtl-loop2
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@opindex fdump-rtl-loop2
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@option{-fdump-rtl-loop2} enables dumping after the
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loop optimization pass, to @file{@var{file}.119r.loop2},
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@file{@var{file}.120r.loop2_init},
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@file{@var{file}.121r.loop2_invariant}, and
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@file{@var{file}.125r.loop2_done}.
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@item -fdump-rtl-sms
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@opindex fdump-rtl-sms
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Dump after modulo scheduling, to @file{@var{file}.136r.sms}.
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@item -fdump-rtl-mach
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@opindex fdump-rtl-mach
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Dump after performing the machine dependent reorganization pass, to
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@file{@var{file}.155r.mach} if that pass exists.
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@item -fdump-rtl-rnreg
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@opindex fdump-rtl-rnreg
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Dump after register renumbering, to @file{@var{file}.147r.rnreg}.
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@item -fdump-rtl-regmove
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@opindex fdump-rtl-regmove
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Dump after the register move pass, to @file{@var{file}.132r.regmove}.
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@item -fdump-rtl-postreload
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@opindex fdump-rtl-postreload
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Dump after post-reload optimizations, to @file{@var{file}.24.postreload}.
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@item -fdump-rtl-expand
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@opindex fdump-rtl-expand
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Dump after RTL generation, to @file{@var{file}.104r.expand}.
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@item -fdump-rtl-sched2
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@opindex fdump-rtl-sched2
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Dump after the second scheduling pass, to @file{@var{file}.149r.sched2}.
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@item -fdump-rtl-cse
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@opindex fdump-rtl-cse
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Dump after CSE (including the jump optimization that sometimes follows
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CSE), to @file{@var{file}.113r.cse}.
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@item -fdump-rtl-sched1
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@opindex fdump-rtl-sched1
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Dump after the first scheduling pass, to @file{@var{file}.136r.sched1}.
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@item -fdump-rtl-cse2
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@opindex fdump-rtl-cse2
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Dump after the second CSE pass (including the jump optimization that
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sometimes follows CSE), to @file{@var{file}.127r.cse2}.
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@item -fdump-rtl-tracer
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@opindex fdump-rtl-tracer
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Dump after running tracer, to @file{@var{file}.118r.tracer}.
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@item -fdump-rtl-vpt
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@itemx -fdump-rtl-vartrack
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@opindex fdump-rtl-vpt
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@opindex fdump-rtl-vartrack
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@option{-fdump-rtl-vpt} enable dumping after the value
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profile transformations, to @file{@var{file}.10.vpt}.
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@option{-fdump-rtl-vartrack} enable dumping after variable tracking,
|
||||
to @file{@var{file}.154r.vartrack}.
|
||||
|
||||
@item -fdump-rtl-flow2
|
||||
@opindex fdump-rtl-flow2
|
||||
Dump after the second flow pass, to @file{@var{file}.142r.flow2}.
|
||||
|
||||
@item -fdump-rtl-peephole2
|
||||
@opindex fdump-rtl-peephole2
|
||||
Dump after the peephole pass, to @file{@var{file}.145r.peephole2}.
|
||||
|
||||
@item -fdump-rtl-web
|
||||
@opindex fdump-rtl-web
|
||||
Dump after live range splitting, to @file{@var{file}.126r.web}.
|
||||
|
||||
@item -fdump-rtl-all
|
||||
@opindex fdump-rtl-all
|
||||
Produce all the dumps listed above.
|
||||
|
||||
@item -dH
|
||||
@opindex dH
|
||||
Produce a core dump whenever an error occurs.
|
||||
|
||||
@ -3332,7 +3332,7 @@ struct rtl_opt_pass pass_convert_to_eh_region_ranges =
|
||||
{
|
||||
{
|
||||
RTL_PASS,
|
||||
"eh-ranges", /* name */
|
||||
"eh_ranges", /* name */
|
||||
NULL, /* gate */
|
||||
convert_to_eh_region_ranges, /* execute */
|
||||
NULL, /* sub */
|
||||
|
||||
@ -1325,7 +1325,7 @@ struct rtl_opt_pass pass_lower_subreg =
|
||||
{
|
||||
{
|
||||
RTL_PASS,
|
||||
"subreg", /* name */
|
||||
"subreg1", /* name */
|
||||
gate_handle_lower_subreg, /* gate */
|
||||
rest_of_handle_lower_subreg, /* execute */
|
||||
NULL, /* sub */
|
||||
|
||||
@ -760,7 +760,7 @@ struct rtl_opt_pass pass_mode_switching =
|
||||
{
|
||||
{
|
||||
RTL_PASS,
|
||||
"mode-sw", /* name */
|
||||
"mode_sw", /* name */
|
||||
gate_mode_switching, /* gate */
|
||||
rest_of_handle_mode_switching, /* execute */
|
||||
NULL, /* sub */
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2009-01-29 Kenneth Zadeck <zadeck@naturalbridge.com>
|
||||
|
||||
PR middle-end/35854
|
||||
* gcc.dg/lower-subreg-1.c: Renamed dump pass from "subreg" to "subreg1"
|
||||
|
||||
2009-01-29 Steve Ellcey <sje@cup.hp.com>
|
||||
|
||||
PR middle-end/38857
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
/* { dg-do compile { target { { { ! mips64 } && { ! ia64-*-* } } && { ! spu-*-* } } } } */
|
||||
/* { dg-options "-O -fdump-rtl-subreg" } */
|
||||
/* { dg-options "-O -fdump-rtl-subreg1" } */
|
||||
/* { dg-require-effective-target ilp32 } */
|
||||
|
||||
long long test (long long a, long long b) { return a | b; }
|
||||
|
||||
/* { dg-final { scan-rtl-dump "Splitting reg" "subreg" } } */
|
||||
/* { dg-final { cleanup-rtl-dump "subreg" } } */
|
||||
/* { dg-final { scan-rtl-dump "Splitting reg" "subreg1" } } */
|
||||
/* { dg-final { cleanup-rtl-dump "subreg1" } } */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user