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Merged in deven-amd/eigen (pull request PR-425)
applying EIGEN_DECLARE_TEST to *gpu unit tests
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commit
038b55464b
@ -395,8 +395,10 @@
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// Means the compiler is HIPCC (analogous to EIGEN_CUDACC, but for HIP)
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#define EIGEN_HIPCC __HIPCC__
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// We need hip_common.h here because __HIP_DEVICE_COMPILE__ is defined in this header.
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#include <hip/hip_common.h>
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// We need to include hip_runtime.h here because it pulls in
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// ++ hip_common.h which contains the define for __HIP_DEVICE_COMPILE__
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// ++ host_defines.h which contains the defines for the __host__ and __device__ macros
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#include <hip/hip_runtime.h>
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#if defined(__HIP_DEVICE_COMPILE__)
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// analogous to EIGEN_CUDA_ARCH, but for HIP
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@ -580,7 +580,7 @@ template<typename T> struct smart_memmove_helper<T,false> {
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// you can overwrite Eigen's default behavior regarding alloca by defining EIGEN_ALLOCA
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// to the appropriate stack allocation function
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#if ! defined EIGEN_ALLOCA && ! defined EIGEN_CUDA_ARCH
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#if ! defined EIGEN_ALLOCA && ! defined EIGEN_GPU_COMPILE_PHASE
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#if EIGEN_OS_LINUX || EIGEN_OS_MAC || (defined alloca)
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#define EIGEN_ALLOCA alloca
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#elif EIGEN_COMP_MSVC
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@ -610,6 +610,7 @@ template<typename SolverType> struct direct_selfadjoint_eigenvalues<SolverType,3
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static inline bool extract_kernel(MatrixType& mat, Ref<VectorType> res, Ref<VectorType> representative)
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{
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EIGEN_USING_STD_MATH(abs);
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EIGEN_USING_STD_MATH(sqrt);
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Index i0;
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// Find non-zero column i0 (by construction, there must exist a non zero coefficient on the diagonal):
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mat.diagonal().cwiseAbs().maxCoeff(&i0);
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@ -620,8 +621,8 @@ template<typename SolverType> struct direct_selfadjoint_eigenvalues<SolverType,3
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VectorType c0, c1;
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n0 = (c0 = representative.cross(mat.col((i0+1)%3))).squaredNorm();
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n1 = (c1 = representative.cross(mat.col((i0+2)%3))).squaredNorm();
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if(n0>n1) res = c0/std::sqrt(n0);
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else res = c1/std::sqrt(n1);
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if(n0>n1) res = c0/sqrt(n0);
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else res = c1/sqrt(n1);
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return true;
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}
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@ -723,7 +724,7 @@ struct direct_selfadjoint_eigenvalues<SolverType,2,false>
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EIGEN_DEVICE_FUNC
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static inline void computeRoots(const MatrixType& m, VectorType& roots)
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{
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using std::sqrt;
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EIGEN_USING_STD_MATH(sqrt);
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const Scalar t0 = Scalar(0.5) * sqrt( numext::abs2(m(0,0)-m(1,1)) + Scalar(4)*numext::abs2(m(1,0)));
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const Scalar t1 = Scalar(0.5) * (m(0,0) + m(1,1));
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roots(0) = t1 - t0;
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@ -449,8 +449,7 @@ struct TensorContractionEvaluatorBase
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// tensor dimensions (i, j) into the original tensor dimensions.
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// TODO(ezhulenev): Add parameters required to infer output tensor index for
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// more complex contractions than 2x2 on internal dimension.
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m_tensor_contraction_params = {
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/**swapped_arguments=*/static_cast<int>(Layout) == RowMajor};
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m_tensor_contraction_params.swapped_arguments = static_cast<int>(Layout) == RowMajor;
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}
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EIGEN_DEVICE_FUNC EIGEN_STRONG_INLINE const Dimensions& dimensions() const { return m_dimensions; }
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@ -1215,16 +1215,16 @@ EigenFloatContractionKernel16x16(const LhsMapper lhs, const RhsMapper rhs,
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}
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template<typename Indices, typename LeftArgType, typename RightArgType>
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struct TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType>, GpuDevice> :
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public TensorContractionEvaluatorBase<TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType>, GpuDevice> > {
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template<typename Indices, typename LeftArgType, typename RightArgType, typename OutputKernelType>
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struct TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType, OutputKernelType>, GpuDevice> :
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public TensorContractionEvaluatorBase<TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType, OutputKernelType>, GpuDevice> > {
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typedef GpuDevice Device;
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typedef TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType>, Device> Self;
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typedef TensorEvaluator<const TensorContractionOp<Indices, LeftArgType, RightArgType, OutputKernelType>, Device> Self;
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typedef TensorContractionEvaluatorBase<Self> Base;
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typedef TensorContractionOp<Indices, LeftArgType, RightArgType> XprType;
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typedef TensorContractionOp<Indices, LeftArgType, RightArgType, OutputKernelType> XprType;
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typedef typename internal::remove_const<typename XprType::Scalar>::type Scalar;
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typedef typename XprType::Index Index;
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typedef typename XprType::CoeffReturnType CoeffReturnType;
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@ -242,7 +242,7 @@ void test_gpu_argmin_dim()
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}
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}
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void test_cxx11_tensor_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_argmax_gpu)
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{
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CALL_SUBTEST_1(test_gpu_simple_argmax<RowMajor>());
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CALL_SUBTEST_1(test_gpu_simple_argmax<ColMajor>());
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@ -72,7 +72,7 @@ void test_fallback_conversion() {
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}
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void test_cxx11_tensor_cast_float16_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_cast_float16_gpu)
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{
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CALL_SUBTEST(test_gpu_conversion());
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CALL_SUBTEST(test_fallback_conversion());
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@ -193,7 +193,7 @@ void test_gpu_contraction_sizes() {
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}
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}
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void test_cxx11_tensor_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_contract_gpu)
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{
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CALL_SUBTEST_1(test_gpu_contraction<ColMajor>(128, 128, 128));
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CALL_SUBTEST_1(test_gpu_contraction<RowMajor>(128, 128, 128));
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@ -389,7 +389,7 @@ void test_gpu() {
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}
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void test_cxx11_tensor_device()
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EIGEN_DECLARE_TEST(cxx11_tensor_device)
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{
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CALL_SUBTEST_1(test_cpu());
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CALL_SUBTEST_2(test_gpu());
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@ -1472,7 +1472,7 @@ void test_gpu_gamma_sample_der_alpha()
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gpuFree(d_out);
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}
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void test_cxx11_tensor_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_gpu)
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{
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CALL_SUBTEST_1(test_gpu_nullary());
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CALL_SUBTEST_1(test_gpu_elementwise_small());
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@ -479,7 +479,7 @@ void test_gpu_forced_evals() {
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#endif
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void test_cxx11_tensor_of_float16_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_of_float16_gpu)
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{
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CALL_SUBTEST_1(test_gpu_numext<void>());
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@ -78,7 +78,7 @@ static void test_complex()
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}
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void test_cxx11_tensor_random_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_random_gpu)
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{
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CALL_SUBTEST(test_gpu_random_uniform());
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CALL_SUBTEST(test_gpu_random_normal());
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@ -134,7 +134,7 @@ static void test_last_dim_reductions() {
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}
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void test_cxx11_tensor_reduction_gpu() {
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EIGEN_DECLARE_TEST(cxx11_tensor_reduction_gpu) {
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CALL_SUBTEST_1((test_full_reductions<float, ColMajor>()));
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CALL_SUBTEST_1((test_full_reductions<double, ColMajor>()));
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CALL_SUBTEST_2((test_full_reductions<float, RowMajor>()));
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@ -71,7 +71,7 @@ void test_gpu_cumsum(int m_size, int k_size, int n_size)
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}
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void test_cxx11_tensor_scan_gpu()
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EIGEN_DECLARE_TEST(cxx11_tensor_scan_gpu)
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{
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CALL_SUBTEST_1(test_gpu_cumsum<ColMajor>(128, 128, 128));
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CALL_SUBTEST_2(test_gpu_cumsum<RowMajor>(128, 128, 128));
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