binutils-gdb/sim/testsuite/h8300/xorw.s
Mike Frysinger 1368b914e9 sim: testsuite: flatten tree
Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.
2021-01-15 19:18:34 -05:00

62 lines
1.5 KiB
ArmAsm

# Hitachi H8 testcase 'xor.w'
# mach(): h8300h h8300s h8sx
# as(h8300): --defsym sim_cpu=0
# as(h8300h): --defsym sim_cpu=1
# as(h8300s): --defsym sim_cpu=2
# as(h8sx): --defsym sim_cpu=3
# ld(h8300h): -m h8300helf
# ld(h8300s): -m h8300self
# ld(h8sx): -m h8300sxelf
.include "testutils.inc"
start
.if (sim_cpu) ; non-zero means h8300h, s, or sx
xor_w_imm16:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w #xx:16,Rd
xor.w #0xffff, r0 ; Immediate 16-bit operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
.endif
test_gr_a5a5 1 ; Make sure other general regs not disturbed
test_gr_a5a5 2
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
.endif
xor_w_reg:
set_grs_a5a5 ; Fill all general regs with a fixed pattern
;; fixme set ccr
;; xor.w Rs,Rd
mov.w #0xffff, r1
xor.w r1, r0 ; Register operand
;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
test_h_gr16 0x5a5a r0 ; xor result: a5a5 ^ ffff
test_h_gr16 0xffff r1 ; Make sure r1 is unchanged
.if (sim_cpu) ; non-zero means h8300h, s, or sx
test_h_gr32 0xa5a55a5a er0 ; xor result: a5a5 ^ ffff
test_h_gr32 0xa5a5ffff er1 ; Make sure er1 is unchanged
.endif
test_gr_a5a5 2 ; Make sure other general regs not disturbed
test_gr_a5a5 3
test_gr_a5a5 4
test_gr_a5a5 5
test_gr_a5a5 6
test_gr_a5a5 7
pass
exit 0