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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
88 lines
2.1 KiB
ArmAsm
88 lines
2.1 KiB
ArmAsm
# Hitachi H8 testcase 'add.w'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# add.w xx:3, rd ; 0 a 0xxx rd (sx only)
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# add.w xx:16, rd ; 7 9 1 rd imm16
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# add.w rs, rd ; 0 9 rs rd
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#
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start
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.if (sim_cpu == h8sx) ; 3-bit immediate mode only for h8sx
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add_w_imm3:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; add.w #xx:3,Rd ; Immediate 3-bit operand
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add.w #7, r0 ; FIXME will not assemble yet
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; .word 0x0a70 ; Fake it until assembler will take it.
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5ac r0 ; add result: a5a5 + 7
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test_h_gr32 0xa5a5a5ac er0 ; add result: a5a5 + 7
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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add_w_imm16:
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;; add.w immediate not available in h8300 mode.
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; add.w #xx:16,Rd
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add.w #0x111, r0 ; Immediate 16-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
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test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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add_w_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; add.w Rs,Rd
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mov.w #0x111, r1
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add.w r1, r0 ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa6b6 r0 ; add result: a5a5 + 111
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test_h_gr16 0x0111 r1
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a6b6 er0 ; add result: a5a5 + 111
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test_h_gr32 0xa5a50111 er1
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.endif
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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pass
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exit 0
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