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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
779 lines
17 KiB
ArmAsm
779 lines
17 KiB
ArmAsm
# Hitachi H8 testcase 'add.b'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# add.b #xx:8, rd ; 8 rd xxxxxxxx
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# add.b #xx:8, @erd ; 7 d rd ???? 8 ???? xxxxxxxx
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# add.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
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# add.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
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# add.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
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# add.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
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# add.b #xx:8, @(d:16, erd) ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
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# add.b #xx:8, @(d:32, erd) ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
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# add.b #xx:8, @aa:8 ; 7 f aaaaaaaa 8 ???? xxxxxxxx
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# add.b #xx:8, @aa:16 ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
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# add.b #xx:8, @aa:32 ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
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# add.b rs, rd ; 0 8 rs rd
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# add.b reg8, @erd ; 7 d rd ???? 0 8 rs ????
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# add.b reg8, @erd+ ; 0 1 7 9 8 rd 1 rs
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# add.b reg8, @erd- ; 0 1 7 9 a rd 1 rs
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# add.b reg8, @+erd ; 0 1 7 9 9 rd 1 rs
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# add.b reg8, @-erd ; 0 1 7 9 b rd 1 rs
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# add.b reg8, @(d:16, erd) ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
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# add.b reg8, @(d:32, erd) ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
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# add.b reg8, @aa:8 ; 7 f aaaaaaaa 0 8 rs ????
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# add.b reg8, @aa:16 ; 6 a 1 1??? aa:16 0 8 rs ????
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# add.b reg8, @aa:32 ; 6 a 3 1??? aa:32 0 8 rs ????
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#
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# Coming soon:
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# add.b #xx:8, @(d:2, erd) ; 0 1 7 b30 | b21 | dd:2, 8 ???? xxxxxxxx
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# add.b reg8, @(d:2, erd) ; 0 1 7 9 dd:2 rd32 1 rs8
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# ...
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.data
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pre_byte: .byte 0
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byte_dest: .byte 0
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post_byte: .byte 0
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start
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add_b_imm8_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; add.b #xx:8,Rd
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add.b #5:8, r0l ; Immediate 8-bit src, reg8 dst
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa5aa r0 ; add result: a5 + 5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a5aa er0 ; add result: a5 + 5
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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add_b_imm8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@eRd
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mov #byte_dest, er0
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add.b #5:8, @er0 ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x7d00
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest, er0 ; er0 still contains address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #5, r0l
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beq .L1
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fail
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.L1:
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add_b_imm8_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@eRd+
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mov #byte_dest, er0
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add.b #5:8, @er0+ ; Immediate 8-bit src, reg post-inc dst
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte, er0 ; er0 contains address plus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #10, r0l
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beq .L2
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fail
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.L2:
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add_b_imm8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@eRd-
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mov #byte_dest, er0
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add.b #5:8, @er0- ; Immediate 8-bit src, reg post-dec dst
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte, er0 ; er0 contains address minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #15, r0l
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beq .L3
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fail
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.L3:
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add_b_imm8_rdpreinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@+eRd
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mov #pre_byte, er0
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add.b #5:8, @+er0 ; Immediate 8-bit src, reg pre-inc dst
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #20, r0l
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beq .L4
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fail
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.L4:
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add_b_imm8_rdpredec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@-eRd
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mov #post_byte, er0
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add.b #5:8, @-er0 ; Immediate 8-bit src, reg pre-dec dst
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;;; .word 0x0177
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;;; .word 0x6c08
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest, er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #25, r0l
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beq .L5
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fail
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.L5:
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add_b_imm8_disp16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@(dd:16, eRd)
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mov #post_byte, er0
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add.b #5:8, @(-1:16, er0) ; Immediate 8-bit src, 16-bit reg disp dest.
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;;; .word 0x0174
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;;; .word 0x6e08
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;;; .word 0xffff
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte, er0 ; er0 contains address plus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #30, r0l
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beq .L6
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fail
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.L6:
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add_b_imm8_disp32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@(dd:32, eRd)
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mov #pre_byte, er0
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add.b #5:8, @(1:32, er0) ; Immediate 8-bit src, 32-bit reg disp. dest.
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;;; .word 0x7804
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;;; .word 0x6a28
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;;; .word 0x0000
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;;; .word 0x0001
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte, er0 ; er0 contains address minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #35, r0l
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beq .L7
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fail
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.L7:
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add_b_imm8_abs8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b reg8,@aa:8
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;; NOTE: for abs8, we will use the SBR register as a base,
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;; since otherwise we would have to make sure that the destination
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;; was in the zero page.
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;;
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mov #byte_dest-100, er0
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ldc er0, sbr
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add.b #5, @100:8 ; 8-bit reg src, 8-bit absolute dest
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;;; .word 0x7f64
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #40, r0l
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beq .L8
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fail
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.L8:
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add_b_imm8_abs16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@aa:16
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add.b #5:8, @byte_dest:16 ; Immediate 8-bit src, 16-bit absolute dest
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;;; .word 0x6a18
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;;; .word byte_dest
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #45, r0l
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beq .L9
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fail
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.L9:
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add_b_imm8_abs32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b #xx:8,@aa:32
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add.b #5:8, @byte_dest:32 ; Immediate 8-bit src, 32-bit absolute dest
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;;; .word 0x6a38
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;;; .long byte_dest
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;;; .word 0x8005
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #50, r0l
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beq .L10
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fail
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.L10:
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.endif
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add_b_reg8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; add.b Rs,Rd
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mov.b #5, r0h
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add.b r0h, r0l ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0x05aa r0 ; add result: a5 + 5
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a505aa er0 ; add result: a5 + 5
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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add_b_reg8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@eRd ; Add to register indirect
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mov #byte_dest, er0
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mov #5, r1l
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add.b r1l, @er0 ; reg8 src, reg indirect dest
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;;; .word 0x7d00
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;;; .word 0x0890
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 still contains address
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #55, r0l
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beq .L11
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fail
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.L11:
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add_b_reg8_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@eRd+ ; Add to register post-increment
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mov #byte_dest, er0
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mov #5, r1l
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add.b r1l, @er0+ ; reg8 src, reg post-incr dest
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;;; .word 0x0179
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;;; .word 0x8019
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte er0 ; er0 contains address plus one
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #60, r0l
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beq .L12
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fail
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.L12:
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add_b_reg8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@eRd- ; Add to register post-decrement
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mov #byte_dest, er0
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mov #5, r1l
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add.b r1l, @er0- ; reg8 src, reg post-decr dest
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;;; .word 0x0179
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;;; .word 0xa019
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte er0 ; er0 contains address minus one
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #65, r0l
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beq .L13
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fail
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.L13:
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add_b_reg8_rdpreinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@+eRd ; Add to register pre-increment
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mov #pre_byte, er0
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mov #5, r1l
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add.b r1l, @+er0 ; reg8 src, reg pre-incr dest
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;;; .word 0x0179
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;;; .word 0x9019
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #70, r0l
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beq .L14
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fail
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.L14:
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add_b_reg8_rdpredec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@-eRd ; Add to register pre-decrement
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mov #post_byte, er0
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mov #5, r1l
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add.b r1l, @-er0 ; reg8 src, reg pre-decr dest
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;;; .word 0x0179
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;;; .word 0xb019
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #75, r0l
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beq .L15
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fail
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.L15:
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add_b_reg8_disp16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@(dd:16, eRd) ; Add to register + 16-bit displacement
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mov #pre_byte, er0
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mov #5, r1l
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add.b r1l, @(1:16, er0) ; reg8 src, 16-bit reg disp dest
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;;; .word 0x0179
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;;; .word 0xc019
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;;; .word 0x0001
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte er0 ; er0 contains address minus one
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #80, r0l
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beq .L16
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fail
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.L16:
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add_b_reg8_disp32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b rs8,@-eRd ; Add to register plus 32-bit displacement
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mov #post_byte, er0
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mov #5, r1l
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add.b r1l, @(-1:32, er0) ; reg8 src, 32-bit reg disp dest
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;;; .word 0x0179
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;;; .word 0xd819
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;;; .word 0xffff
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;;; .word 0xffff
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte er0 ; er0 contains address plus one
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test_h_gr32 0xa5a5a505 er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #85, r0l
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beq .L17
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fail
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.L17:
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add_b_reg8_abs8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b reg8,@aa:8
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;; NOTE: for abs8, we will use the SBR register as a base,
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;; since otherwise we would have to make sure that the destination
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;; was in the zero page.
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;;
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mov #byte_dest-100, er0
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ldc er0, sbr
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mov #5, r1l
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add.b r1l, @100:8 ; 8-bit reg src, 8-bit absolute dest
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;;; .word 0x7f64
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;;; .word 0x0890
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest-100, er0 ; reg 0 has base address
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test_h_gr32 0xa5a5a505 er1 ; reg 1 has test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #90, r0l
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beq .L18
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fail
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.L18:
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add_b_reg8_abs16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b reg8,@aa:16
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mov #5, r0l
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add.b r0l, @byte_dest:16 ; 8-bit reg src, 16-bit absolute dest
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;;; .word 0x6a18
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;;; .word byte_dest
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;;; .word 0x0880
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #95, r0l
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beq .L19
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fail
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.L19:
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add_b_reg8_abs32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; add.b reg8,@aa:32
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mov #5, r0l
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add.b r0l, @byte_dest:32 ; 8-bit reg src, 32-bit absolute dest
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;;; .word 0x6a38
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;;; .long byte_dest
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;;; .word 0x0880
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
|
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test_zero_clear
|
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test_neg_clear
|
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|
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test_h_gr32 0xa5a5a505 er0 ; reg 0 has test load
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
|
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the add to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #100, r0l
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beq .L20
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fail
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.L20:
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.endif
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pass
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exit 0
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