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297 lines
7.6 KiB
C
297 lines
7.6 KiB
C
/* Blackfin General Purpose Ports (GPIO) model
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For "new style" GPIOs on BF54x parts.
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Copyright (C) 2010-2021 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc. and Mike Frysinger.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_gpio2.h"
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struct bfin_gpio
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{
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bu32 base;
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/* Only accessed indirectly via dir_{set,clear}. */
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bu16 dir;
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/* Make sure hardware MMRs are aligned. */
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bu16 _pad;
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/* Order after here is important -- matches hardware MMR layout. */
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bu16 BFIN_MMR_16(fer);
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bu16 BFIN_MMR_16(data);
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bu16 BFIN_MMR_16(set);
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bu16 BFIN_MMR_16(clear);
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bu16 BFIN_MMR_16(dir_set);
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bu16 BFIN_MMR_16(dir_clear);
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bu16 BFIN_MMR_16(inen);
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bu32 mux;
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};
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#define mmr_base() offsetof(struct bfin_gpio, fer)
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#define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"PORTIO_FER", "PORTIO", "PORTIO_SET", "PORTIO_CLEAR", "PORTIO_DIR_SET",
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"PORTIO_DIR_CLEAR", "PORTIO_INEN", "PORTIO_MUX",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static unsigned
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bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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mmr_off = addr - port->base;
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/* Invalid access mode is higher priority than missing register. */
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if (mmr_off == mmr_offset (mux))
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{
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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}
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else
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
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return 0;
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if (nr_bytes == 4)
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value = dv_load_4 (source);
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else
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value = dv_load_2 (source);
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(fer):
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case mmr_offset(data):
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case mmr_offset(inen):
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*value16p = value;
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break;
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case mmr_offset(clear):
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/* We want to clear the related data MMR. */
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dv_w1c_2 (&port->data, value, -1);
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break;
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case mmr_offset(set):
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/* We want to set the related data MMR. */
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port->data |= value;
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break;
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case mmr_offset(dir_clear):
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dv_w1c_2 (&port->dir, value, -1);
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break;
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case mmr_offset(dir_set):
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port->dir |= value;
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break;
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case mmr_offset(mux):
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*value32p = value;
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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return 0;
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}
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/* If tweaking output pins, make sure we send updated port info. */
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(set):
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case mmr_offset(clear):
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case mmr_offset(dir_set):
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{
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int i;
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bu32 bit;
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for (i = 0; i < 16; ++i)
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{
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bit = (1 << i);
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if (!(port->inen & bit))
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hw_port_event (me, i, !!(port->data & bit));
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}
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break;
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}
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}
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return nr_bytes;
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}
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static unsigned
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bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space,
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address_word addr, unsigned nr_bytes)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 mmr_off;
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bu16 *value16p;
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bu32 *value32p;
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void *valuep;
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mmr_off = addr - port->base;
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/* Invalid access mode is higher priority than missing register. */
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if (mmr_off == mmr_offset (mux))
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{
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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}
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else
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if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
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return 0;
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valuep = (void *)((unsigned long)port + mmr_base() + mmr_off);
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value16p = valuep;
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value32p = valuep;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(data):
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case mmr_offset(clear):
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case mmr_offset(set):
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dv_store_2 (dest, port->data);
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break;
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case mmr_offset(dir_clear):
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case mmr_offset(dir_set):
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dv_store_2 (dest, port->dir);
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break;
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case mmr_offset(fer):
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case mmr_offset(inen):
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dv_store_2 (dest, *value16p);
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break;
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case mmr_offset(mux):
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dv_store_4 (dest, *value32p);
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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return 0;
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}
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_gpio_ports[] =
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{
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{ "p0", 0, 0, bidirect_port, },
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{ "p1", 1, 0, bidirect_port, },
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{ "p2", 2, 0, bidirect_port, },
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{ "p3", 3, 0, bidirect_port, },
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{ "p4", 4, 0, bidirect_port, },
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{ "p5", 5, 0, bidirect_port, },
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{ "p6", 6, 0, bidirect_port, },
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{ "p7", 7, 0, bidirect_port, },
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{ "p8", 8, 0, bidirect_port, },
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{ "p9", 9, 0, bidirect_port, },
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{ "p10", 10, 0, bidirect_port, },
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{ "p11", 11, 0, bidirect_port, },
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{ "p12", 12, 0, bidirect_port, },
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{ "p13", 13, 0, bidirect_port, },
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{ "p14", 14, 0, bidirect_port, },
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{ "p15", 15, 0, bidirect_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source,
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int source_port, int level)
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{
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struct bfin_gpio *port = hw_data (me);
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bu32 bit = (1 << my_port);
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/* Normalize the level value. A simulated device can send any value
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it likes to us, but in reality we only care about 0 and 1. This
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lets us assume only those two values below. */
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level = !!level;
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HW_TRACE ((me, "pin %i set to %i", my_port, level));
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/* Only screw with state if this pin is set as an input, and the
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input is actually enabled, and it isn't in peripheral mode. */
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if ((port->dir & bit) || !(port->inen & bit) || !(port->fer & bit))
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{
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HW_TRACE ((me, "ignoring level due to DIR=%i INEN=%i FER=%i",
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!!(port->dir & bit), !!(port->inen & bit),
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!!(port->fer & bit)));
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return;
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}
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hw_port_event (me, my_port, level);
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}
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static void
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attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_MMR_GPIO2_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO2_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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port->base = attach_address;
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}
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static void
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bfin_gpio_finish (struct hw *me)
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{
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struct bfin_gpio *port;
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port = HW_ZALLOC (me, struct bfin_gpio);
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set_hw_data (me, port);
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set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer);
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set_hw_ports (me, bfin_gpio_ports);
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set_hw_port_event (me, bfin_gpio_port_event);
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attach_bfin_gpio_regs (me, port);
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}
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const struct hw_descriptor dv_bfin_gpio2_descriptor[] =
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{
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{"bfin_gpio2", bfin_gpio_finish,},
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{NULL, NULL},
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};
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