mirror of
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a2c5833233
The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out */po/*.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.
743 lines
21 KiB
Plaintext
743 lines
21 KiB
Plaintext
@c Copyright (C) 2000-2022 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node ARC-Dependent
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@chapter ARC Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter ARC Dependent Features
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@end ifclear
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@set ARC_CORE_DEFAULT 6
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@cindex ARC support
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@menu
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* ARC Options:: Options
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* ARC Syntax:: Syntax
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* ARC Directives:: ARC Machine Directives
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* ARC Modifiers:: ARC Assembler Modifiers
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* ARC Symbols:: ARC Pre-defined Symbols
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* ARC Opcodes:: Opcodes
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@end menu
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@node ARC Options
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@section Options
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@cindex ARC options
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@cindex options for ARC
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The following options control the type of CPU for which code is
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assembled, and generic constraints on the code generated:
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@table @code
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@item -mcpu=@var{cpu}
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@cindex @code{-mcpu=@var{cpu}} command-line option, ARC
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Set architecture type and register usage for @var{cpu}. There are
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also shortcut alias options available for backward compatibility and
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convenience. Supported values for @var{cpu} are
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@table @code
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@cindex @code{mA6} command-line option, ARC
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@cindex @code{marc600} command-line option, ARC
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@item arc600
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Assemble for ARC 600. Aliases: @code{-mA6}, @code{-mARC600}.
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@item arc600_norm
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Assemble for ARC 600 with norm instructions.
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@item arc600_mul64
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Assemble for ARC 600 with mul64 instructions.
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@item arc600_mul32x16
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Assemble for ARC 600 with mul32x16 instructions.
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@item arc601
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@cindex @code{mARC601} command-line option, ARC
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Assemble for ARC 601. Alias: @code{-mARC601}.
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@item arc601_norm
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Assemble for ARC 601 with norm instructions.
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@item arc601_mul64
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Assemble for ARC 601 with mul64 instructions.
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@item arc601_mul32x16
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Assemble for ARC 601 with mul32x16 instructions.
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@item arc700
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@cindex @code{mA7} command-line option, ARC
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@cindex @code{mARC700} command-line option, ARC
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Assemble for ARC 700. Aliases: @code{-mA7}, @code{-mARC700}.
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@item arcem
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@cindex @code{mEM} command-line option, ARC
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Assemble for ARC EM. Aliases: @code{-mEM}
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@item em
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Assemble for ARC EM, identical as arcem variant.
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@item em4
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Assemble for ARC EM with code-density instructions.
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@item em4_dmips
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Assemble for ARC EM with code-density instructions.
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@item em4_fpus
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Assemble for ARC EM with code-density instructions.
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@item em4_fpuda
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Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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@item quarkse_em
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Assemble for QuarkSE-EM cpu.
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@item archs
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@cindex @code{mHS} command-line option, ARC
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Assemble for ARC HS. Aliases: @code{-mHS}, @code{-mav2hs}.
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@item hs
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Assemble for ARC HS.
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@item hs34
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Assemble for ARC HS34.
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@item hs38
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Assemble for ARC HS38.
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@item hs38_linux
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Assemble for ARC HS38 with floating point support on.
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@item nps400
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@cindex @code{mnps400} command-line option, ARC
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Assemble for ARC 700 with NPS-400 extended instructions.
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@end table
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Note: the @code{.cpu} directive (@pxref{ARC Directives}) can
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to be used to select a core variant from within assembly code.
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@cindex @code{-EB} command-line option, ARC
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@item -EB
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a big-endian processor.
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@cindex @code{-EL} command-line option, ARC
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@item -EL
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This option specifies that the output generated by the assembler should
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be marked as being encoded for a little-endian processor - this is the
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default.
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@cindex @code{-mcode-density} command-line option, ARC
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@item -mcode-density
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This option turns on Code Density instructions. Only valid for ARC EM
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processors.
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@cindex @code{-mrelax} command-line option, ARC
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@item -mrelax
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Enable support for assembly-time relaxation. The assembler will
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replace a longer version of an instruction with a shorter one,
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whenever it is possible.
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@cindex @code{-mnps400} command-line option, ARC
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@item -mnps400
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Enable support for NPS-400 extended instructions.
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@cindex @code{-mspfp} command-line option, ARC
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@item -mspfp
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Enable support for single-precision floating point instructions.
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@cindex @code{-mdpfp} command-line option, ARC
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@item -mdpfp
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Enable support for double-precision floating point instructions.
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@cindex @code{-mfpuda} command-line option, ARC
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@item -mfpuda
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Enable support for double-precision assist floating point instructions.
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Only valid for ARC EM processors.
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@end table
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@node ARC Syntax
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@section Syntax
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@menu
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* ARC-Chars:: Special Characters
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* ARC-Regs:: Register Names
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@end menu
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@node ARC-Chars
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@subsection Special Characters
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@table @code
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@item %
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@cindex register name prefix character, ARC
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@cindex ARC register name prefix character
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A register name can optionally be prefixed by a @samp{%} character. So
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register @code{%r0} is equivalent to @code{r0} in the assembly code.
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@item #
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@cindex line comment character, ARC
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@cindex ARC line comment character
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The presence of a @samp{#} character within a line (but not at the
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start of a line) indicates the start of a comment that extends to the
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end of the current line.
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@emph{Note:} if a line starts with a @samp{#} character then it can
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also be a logical line number directive (@pxref{Comments}) or a
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preprocessor control command (@pxref{Preprocessing}).
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@item @@
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@cindex symbol prefix character, ARC
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@cindex ARC symbol prefix character
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Prefixing an operand with an @samp{@@} specifies that the operand is a
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symbol and not a register. This is how the assembler disambiguates
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the use of an ARC register name as a symbol. So the instruction
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@example
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mov r0, @@r0
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@end example
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moves the address of symbol @code{r0} into register @code{r0}.
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@item `
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@cindex line separator, ARC
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@cindex statement separator, ARC
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@cindex ARC line separator
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The @samp{`} (backtick) character is used to separate statements on a
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single line.
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@cindex line
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@item -
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@cindex C preprocessor macro separator, ARC
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@cindex ARC C preprocessor macro separator
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Used as a separator to obtain a sequence of commands from a C
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preprocessor macro.
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@end table
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@node ARC-Regs
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@subsection Register Names
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@cindex ARC register names
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@cindex register names, ARC
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The ARC assembler uses the following register names for its core
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registers:
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@table @code
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@item r0-r31
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@cindex core general registers, ARC
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@cindex ARC core general registers
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The core general registers. Registers @code{r26} through @code{r31}
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have special functions, and are usually referred to by those synonyms.
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@item gp
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@cindex global pointer, ARC
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@cindex ARC global pointer
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The global pointer and a synonym for @code{r26}.
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@item fp
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@cindex frame pointer, ARC
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@cindex ARC frame pointer
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The frame pointer and a synonym for @code{r27}.
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@item sp
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@cindex stack pointer, ARC
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@cindex ARC stack pointer
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The stack pointer and a synonym for @code{r28}.
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@item ilink1
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@cindex level 1 interrupt link register, ARC
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@cindex ARC level 1 interrupt link register
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For ARC 600 and ARC 700, the level 1 interrupt link register and a
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synonym for @code{r29}. Not supported for ARCv2.
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@item ilink
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@cindex interrupt link register, ARC
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@cindex ARC interrupt link register
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For ARCv2, the interrupt link register and a synonym for @code{r29}.
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Not supported for ARC 600 and ARC 700.
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@item ilink2
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@cindex level 2 interrupt link register, ARC
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@cindex ARC level 2 interrupt link register
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For ARC 600 and ARC 700, the level 2 interrupt link register and a
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synonym for @code{r30}. Not supported for ARC v2.
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@item blink
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@cindex link register, ARC
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@cindex ARC link register
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The link register and a synonym for @code{r31}.
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@item r32-r59
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@cindex extension core registers, ARC
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@cindex ARC extension core registers
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The extension core registers.
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@item lp_count
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@cindex loop counter, ARC
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@cindex ARC loop counter
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The loop count register.
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@item pcl
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@cindex word aligned program counter, ARC
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@cindex ARC word aligned program counter
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The word aligned program counter.
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@end table
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In addition the ARC processor has a large number of @emph{auxiliary
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registers}. The precise set depends on the extensions being
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supported, but the following baseline set are always defined:
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@table @code
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@item identity
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@cindex Processor Identification register, ARC
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@cindex ARC Processor Identification register
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Processor Identification register. Auxiliary register address 0x4.
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@item pc
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@cindex Program Counter, ARC
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@cindex ARC Program Counter
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Program Counter. Auxiliary register address 0x6.
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@item status32
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@cindex Status register, ARC
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@cindex ARC Status register
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Status register. Auxiliary register address 0x0a.
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@item bta
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@cindex Branch Target Address, ARC
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@cindex ARC Branch Target Address
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Branch Target Address. Auxiliary register address 0x412.
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@item ecr
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@cindex Exception Cause Register, ARC
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@cindex ARC Exception Cause Register
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Exception Cause Register. Auxiliary register address 0x403.
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@item int_vector_base
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@cindex Interrupt Vector Base address, ARC
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@cindex ARC Interrupt Vector Base address
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Interrupt Vector Base address. Auxiliary register address 0x25.
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@item status32_p0
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@cindex Stored STATUS32 register on entry to level P0 interrupts, ARC
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@cindex ARC Stored STATUS32 register on entry to level P0 interrupts
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Stored STATUS32 register on entry to level P0 interrupts. Auxiliary
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register address 0xb.
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@item aux_user_sp
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@cindex Saved User Stack Pointer, ARC
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@cindex ARC Saved User Stack Pointer
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Saved User Stack Pointer. Auxiliary register address 0xd.
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@item eret
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@cindex Exception Return Address, ARC
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@cindex ARC Exception Return Address
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Exception Return Address. Auxiliary register address 0x400.
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@item erbta
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@cindex BTA saved on exception entry, ARC
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@cindex ARC BTA saved on exception entry
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BTA saved on exception entry. Auxiliary register address 0x401.
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@item erstatus
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@cindex STATUS32 saved on exception, ARC
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@cindex ARC STATUS32 saved on exception
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STATUS32 saved on exception. Auxiliary register address 0x402.
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@item bcr_ver
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@cindex Build Configuration Registers Version, ARC
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@cindex ARC Build Configuration Registers Version
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Build Configuration Registers Version. Auxiliary register address 0x60.
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@item bta_link_build
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@cindex Build configuration for: BTA Registers, ARC
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@cindex ARC Build configuration for: BTA Registers
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Build configuration for: BTA Registers. Auxiliary register address 0x63.
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@item vecbase_ac_build
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@cindex Build configuration for: Interrupts, ARC
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@cindex ARC Build configuration for: Interrupts
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Build configuration for: Interrupts. Auxiliary register address 0x68.
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@item rf_build
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@cindex Build configuration for: Core Registers, ARC
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@cindex ARC Build configuration for: Core Registers
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Build configuration for: Core Registers. Auxiliary register address 0x6e.
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@item dccm_build
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@cindex DCCM RAM Configuration Register, ARC
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@cindex ARC DCCM RAM Configuration Register
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DCCM RAM Configuration Register. Auxiliary register address 0xc1.
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@end table
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Additional auxiliary register names are defined according to the
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processor architecture version and extensions selected by the options.
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@node ARC Directives
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@section ARC Machine Directives
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@cindex machine directives, ARC
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@cindex ARC machine directives
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The ARC version of @code{@value{AS}} supports the following additional
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machine directives:
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@table @code
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@cindex @code{lcomm} directive
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@item .lcomm @var{symbol}, @var{length}[, @var{alignment}]
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Reserve @var{length} (an absolute expression) bytes for a local common
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denoted by @var{symbol}. The section and value of @var{symbol} are
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those of the new local common. The addresses are allocated in the bss
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section, so that at run-time the bytes start off zeroed. Since
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@var{symbol} is not declared global, it is normally not visible to
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@code{@value{LD}}. The optional third parameter, @var{alignment},
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specifies the desired alignment of the symbol in the bss section,
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specified as a byte boundary (for example, an alignment of 16 means
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that the least significant 4 bits of the address should be zero). The
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alignment must be an absolute expression, and it must be a power of
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two. If no alignment is specified, as will set the alignment to the
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largest power of two less than or equal to the size of the symbol, up
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to a maximum of 16.
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@cindex @code{lcommon} directive, ARC
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@item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
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The same as @code{lcomm} directive.
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@cindex @code{cpu} directive, ARC
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@item .cpu @var{cpu}
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The @code{.cpu} directive must be followed by the desired core
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version. Permitted values for CPU are:
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@table @code
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@item ARC600
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Assemble for the ARC600 instruction set.
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@item arc600_norm
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Assemble for ARC 600 with norm instructions.
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@item arc600_mul64
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Assemble for ARC 600 with mul64 instructions.
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@item arc600_mul32x16
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Assemble for ARC 600 with mul32x16 instructions.
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@item arc601
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Assemble for ARC 601 instruction set.
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@item arc601_norm
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Assemble for ARC 601 with norm instructions.
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@item arc601_mul64
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Assemble for ARC 601 with mul64 instructions.
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@item arc601_mul32x16
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Assemble for ARC 601 with mul32x16 instructions.
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@item ARC700
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Assemble for the ARC700 instruction set.
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@item NPS400
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Assemble for the NPS400 instruction set.
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@item EM
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Assemble for the ARC EM instruction set.
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@item arcem
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Assemble for ARC EM instruction set
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@item em4
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Assemble for ARC EM with code-density instructions.
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@item em4_dmips
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Assemble for ARC EM with code-density instructions.
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@item em4_fpus
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Assemble for ARC EM with code-density instructions.
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@item em4_fpuda
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Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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@item quarkse_em
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Assemble for QuarkSE-EM instruction set.
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@item HS
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Assemble for the ARC HS instruction set.
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@item archs
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Assemble for ARC HS instruction set.
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@item hs
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Assemble for ARC HS instruction set.
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@item hs34
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Assemble for ARC HS34 instruction set.
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@item hs38
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Assemble for ARC HS38 instruction set.
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@item hs38_linux
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Assemble for ARC HS38 with floating point support on.
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@end table
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Note: the @code{.cpu} directive overrides the command-line option
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@code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
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consistent between the two.
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@item .extAuxRegister @var{name}, @var{addr}, @var{mode}
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@cindex @code{extAuxRegister} directive, ARC
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Auxiliary registers can be defined in the assembler source code by
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using this directive. The first parameter, @var{name}, is the name of the
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new auxiliary register. The second parameter, @var{addr}, is
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address the of the auxiliary register. The third parameter,
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@var{mode}, specifies whether the register is readable and/or writable
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and is one of:
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@table @code
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@item r
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Read only;
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@item w
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Write only;
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@item r|w
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Read and write.
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@end table
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For example:
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@example
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.extAuxRegister mulhi, 0x12, w
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@end example
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specifies a write only extension auxiliary register, @var{mulhi} at
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address 0x12.
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@item .extCondCode @var{suffix}, @var{val}
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@cindex @code{extCondCode} directive, ARC
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ARC supports extensible condition codes. This directive defines a new
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condition code, to be known by the suffix, @var{suffix} and will
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depend on the value, @var{val} in the condition code.
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For example:
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@example
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.extCondCode is_busy,0x14
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add.is_busy r1,r2,r3
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@end example
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will only execute the @code{add} instruction if the condition code
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value is 0x14.
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@item .extCoreRegister @var{name}, @var{regnum}, @var{mode}, @var{shortcut}
|
|
@cindex @code{extCoreRegister} directive, ARC
|
|
Specifies an extension core register named @var{name} as a synonym for
|
|
the register numbered @var{regnum}. The register number must be
|
|
between 32 and 59. The third argument, @var{mode}, indicates whether
|
|
the register is readable and/or writable and is one of:
|
|
@table @code
|
|
@item r
|
|
Read only;
|
|
|
|
@item w
|
|
Write only;
|
|
|
|
@item r|w
|
|
Read and write.
|
|
|
|
@end table
|
|
|
|
The final parameter, @var{shortcut} indicates whether the register has
|
|
a short cut in the pipeline. The valid values are:
|
|
@table @code
|
|
@item can_shortcut
|
|
The register has a short cut in the pipeline;
|
|
|
|
@item cannot_shortcut
|
|
The register does not have a short cut in the pipeline.
|
|
@end table
|
|
|
|
For example:
|
|
@example
|
|
.extCoreRegister mlo, 57, r , can_shortcut
|
|
@end example
|
|
defines a read only extension core register, @code{mlo}, which is
|
|
register 57, and can short cut the pipeline.
|
|
|
|
@item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
|
|
@cindex @code{extInstruction} directive, ARC
|
|
ARC allows the user to specify extension instructions. These
|
|
extension instructions are not macros; the assembler creates encodings
|
|
for use of these instructions according to the specification by the
|
|
user.
|
|
|
|
The first argument, @var{name}, gives the name of the instruction.
|
|
|
|
The second argument, @var{opcode}, is the opcode to be used (bits 31:27
|
|
in the encoding).
|
|
|
|
The third argument, @var{subopcode}, is the sub-opcode to be used, but
|
|
the correct value also depends on the fifth argument,
|
|
@var{syntaxclass}
|
|
|
|
The fourth argument, @var{suffixclass}, determines the kinds of
|
|
suffixes to be allowed. Valid values are:
|
|
@table @code
|
|
@item SUFFIX_NONE
|
|
No suffixes are permitted;
|
|
|
|
@item SUFFIX_COND
|
|
Conditional suffixes are permitted;
|
|
|
|
@item SUFFIX_FLAG
|
|
Flag setting suffixes are permitted.
|
|
|
|
@item SUFFIX_COND|SUFFIX_FLAG
|
|
Both conditional and flag setting suffices are permitted.
|
|
|
|
@end table
|
|
|
|
The fifth and final argument, @var{syntaxclass}, determines the syntax
|
|
class for the instruction. It can have the following values:
|
|
@table @code
|
|
@item SYNTAX_2OP
|
|
Two Operand Instruction;
|
|
|
|
@item SYNTAX_3OP
|
|
Three Operand Instruction.
|
|
|
|
@item SYNTAX_1OP
|
|
One Operand Instruction.
|
|
|
|
@item SYNTAX_NOP
|
|
No Operand Instruction.
|
|
@end table
|
|
|
|
The syntax class may be followed by @samp{|} and one of the following
|
|
modifiers.
|
|
@table @code
|
|
|
|
@item OP1_MUST_BE_IMM
|
|
Modifies syntax class @code{SYNTAX_3OP}, specifying that the first
|
|
operand of a three-operand instruction must be an immediate (i.e., the
|
|
result is discarded). This is usually used to set the flags using
|
|
specific instructions and not retain results.
|
|
|
|
@item OP1_IMM_IMPLIED
|
|
Modifies syntax class @code{SYNTAX_20P}, specifying that there is an
|
|
implied immediate destination operand which does not appear in the
|
|
syntax.
|
|
|
|
For example, if the source code contains an instruction like:
|
|
@example
|
|
inst r1,r2
|
|
@end example
|
|
the first argument is an implied immediate (that is, the result is
|
|
discarded). This is the same as though the source code were: inst
|
|
0,r1,r2.
|
|
|
|
@end table
|
|
|
|
For example, defining a 64-bit multiplier with immediate operands:
|
|
@example
|
|
.extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
|
|
SYNTAX_3OP|OP1_MUST_BE_IMM
|
|
@end example
|
|
which specifies an extension instruction named @code{mp64} with 3
|
|
operands. It sets the flags and can be used with a condition code,
|
|
for which the first operand is an immediate, i.e. equivalent to
|
|
discarding the result of the operation.
|
|
|
|
A two operands instruction variant would be:
|
|
@example
|
|
.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
|
|
SYNTAX_2OP|OP1_IMM_IMPLIED
|
|
@end example
|
|
which describes a two operand instruction with an implicit first
|
|
immediate operand. The result of this operation would be discarded.
|
|
|
|
@cindex @code{.arc_attribute} directive, ARC
|
|
@item .arc_attribute @var{tag}, @var{value}
|
|
Set the ARC object attribute @var{tag} to @var{value}.
|
|
|
|
The @var{tag} is either an attribute number, or one of the following:
|
|
@code{Tag_ARC_PCS_config}, @code{Tag_ARC_CPU_base},
|
|
@code{Tag_ARC_CPU_variation}, @code{Tag_ARC_CPU_name},
|
|
@code{Tag_ARC_ABI_rf16}, @code{Tag_ARC_ABI_osver}, @code{Tag_ARC_ABI_sda},
|
|
@code{Tag_ARC_ABI_pic}, @code{Tag_ARC_ABI_tls}, @code{Tag_ARC_ABI_enumsize},
|
|
@code{Tag_ARC_ABI_exceptions}, @code{Tag_ARC_ABI_double_size},
|
|
@code{Tag_ARC_ISA_config}, @code{Tag_ARC_ISA_apex},
|
|
@code{Tag_ARC_ISA_mpy_option}
|
|
|
|
The @var{value} is either a @code{number}, @code{"string"}, or
|
|
@code{number, "string"} depending on the tag.
|
|
|
|
@end table
|
|
|
|
@node ARC Modifiers
|
|
@section ARC Assembler Modifiers
|
|
|
|
The following additional assembler modifiers have been added for
|
|
position-independent code. These modifiers are available only with
|
|
the ARC 700 and above processors and generate relocation entries,
|
|
which are interpreted by the linker as follows:
|
|
|
|
@table @code
|
|
@item @@pcl(@var{symbol})
|
|
@cindex @@pcl(@var{symbol}), ARC modifier
|
|
Relative distance of @var{symbol}'s from the current program counter
|
|
location.
|
|
|
|
@item @@gotpc(@var{symbol})
|
|
@cindex @@gotpc(@var{symbol}), ARC modifier
|
|
Relative distance of @var{symbol}'s Global Offset Table entry from the
|
|
current program counter location.
|
|
|
|
@item @@gotoff(@var{symbol})
|
|
@cindex @@gotoff(@var{symbol}), ARC modifier
|
|
Distance of @var{symbol} from the base of the Global Offset Table.
|
|
|
|
@item @@plt(@var{symbol})
|
|
@cindex @@plt(@var{symbol}), ARC modifier
|
|
Distance of @var{symbol}'s Procedure Linkage Table entry from the
|
|
current program counter. This is valid only with branch and link
|
|
instructions and PC-relative calls.
|
|
|
|
@item @@sda(@var{symbol})
|
|
@cindex @@sda(@var{symbol}), ARC modifier
|
|
Relative distance of @var{symbol} from the base of the Small Data
|
|
Pointer.
|
|
|
|
@end table
|
|
|
|
@node ARC Symbols
|
|
@section ARC Pre-defined Symbols
|
|
|
|
The following assembler symbols will prove useful when developing
|
|
position-independent code. These symbols are available only with the
|
|
ARC 700 and above processors.
|
|
|
|
@table @code
|
|
@item __GLOBAL_OFFSET_TABLE__
|
|
@cindex __GLOBAL_OFFSET_TABLE__, ARC pre-defined symbol
|
|
Symbol referring to the base of the Global Offset Table.
|
|
|
|
@item __DYNAMIC__
|
|
@cindex __DYNAMIC__, ARC pre-defined symbol
|
|
An alias for the Global Offset Table
|
|
@code{Base__GLOBAL_OFFSET_TABLE__}. It can be used only with
|
|
@code{@@gotpc} modifiers.
|
|
|
|
@end table
|
|
|
|
@node ARC Opcodes
|
|
@section Opcodes
|
|
|
|
@cindex ARC opcodes
|
|
@cindex opcodes for ARC
|
|
|
|
For information on the ARC instruction set, see @cite{ARC Programmers
|
|
Reference Manual}, available where you download the processor IP library.
|