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This commits the result of running gdb/copyright.py as per our Start
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gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/* Copyright 2016-2021 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of the PRU simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#ifndef PRU_H
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#define PRU_H
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#include "config.h"
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#include "opcode/pru.h"
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/* Needed for handling the dual PRU address space. */
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#define IMEM_ADDR_MASK ((1u << 23) - 1)
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#define IMEM_ADDR_DEFAULT 0x20000000
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/* Define memory sizes to allocate for simulated target. Sizes are
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artificially large to accommodate execution of compiler test suite.
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Please synchronize with the linker script for prusim target. */
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#define DMEM_DEFAULT_SIZE (64 * 1024 * 1024)
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/* 16-bit word addressable space. */
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#define IMEM_DEFAULT_SIZE (64 * 4 * 1024)
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/* For AM335x SoCs. */
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#define XFRID_SCRATCH_BANK_0 10
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#define XFRID_SCRATCH_BANK_1 11
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#define XFRID_SCRATCH_BANK_2 12
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#define XFRID_SCRATCH_BANK_PEER 14
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#define XFRID_MAX 255
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#define CPU (cpu->pru_cpu)
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#define PC (CPU.pc)
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#define PC_byteaddr ((PC << 2) | PC_ADDR_SPACE_MARKER)
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/* Various opcode fields. */
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#define RS1 extract_regval (CPU.regs[GET_INSN_FIELD (RS1, inst)], \
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GET_INSN_FIELD (RS1SEL, inst))
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#define RS2 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
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GET_INSN_FIELD (RS2SEL, inst))
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#define RS2_w0 extract_regval (CPU.regs[GET_INSN_FIELD (RS2, inst)], \
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RSEL_15_0)
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#define XBBO_BASEREG (CPU.regs[GET_INSN_FIELD (RS1, inst)])
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#define RS1SEL GET_INSN_FIELD (RS1SEL, inst)
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#define RS1_WIDTH regsel_width (RS1SEL)
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#define RDSEL GET_INSN_FIELD (RDSEL, inst)
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#define RD_WIDTH regsel_width (RDSEL)
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#define RD_REGN GET_INSN_FIELD (RD, inst)
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#define IO GET_INSN_FIELD (IO, inst)
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#define IMM8 GET_INSN_FIELD (IMM8, inst)
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#define IMM16 GET_INSN_FIELD (IMM16, inst)
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#define WAKEONSTATUS GET_INSN_FIELD (WAKEONSTATUS, inst)
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#define CB GET_INSN_FIELD (CB, inst)
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#define RDB GET_INSN_FIELD (RDB, inst)
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#define XFR_WBA GET_INSN_FIELD (XFR_WBA, inst)
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#define LOOP_JMPOFFS GET_INSN_FIELD (LOOP_JMPOFFS, inst)
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#define BROFF ((uint32_t) GET_BROFF_SIGNED (inst))
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#define _BURSTLEN_CALCULATE(BITFIELD) \
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((BITFIELD) >= LSSBBO_BYTECOUNT_R0_BITS7_0 ? \
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(CPU.regs[0] >> ((BITFIELD) - LSSBBO_BYTECOUNT_R0_BITS7_0) * 8) & 0xff \
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: (BITFIELD) + 1)
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#define BURSTLEN _BURSTLEN_CALCULATE (GET_BURSTLEN (inst))
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#define XFR_LENGTH _BURSTLEN_CALCULATE (GET_INSN_FIELD (XFR_LENGTH, inst))
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#define DO_XIN(wba,regn,rdb,l) \
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pru_sim_xin (sd, cpu, (wba), (regn), (rdb), (l))
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#define DO_XOUT(wba,regn,rdb,l) \
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pru_sim_xout (sd, cpu, (wba), (regn), (rdb), (l))
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#define DO_XCHG(wba,regn,rdb,l) \
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pru_sim_xchg (sd, cpu, (wba), (regn), (rdb), (l))
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#define RAISE_SIGILL(sd) sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
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sim_stopped, SIM_SIGILL)
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#define RAISE_SIGINT(sd) sim_engine_halt ((sd), NULL, NULL, PC_byteaddr, \
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sim_stopped, SIM_SIGINT)
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#define MAC_R25_MAC_MODE_MASK (1u << 0)
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#define MAC_R25_ACC_CARRY_MASK (1u << 1)
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#define CARRY CPU.carry
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#define CTABLE CPU.ctable
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#define PC_ADDR_SPACE_MARKER CPU.pc_addr_space_marker
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#define LOOPTOP CPU.loop.looptop
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#define LOOPEND CPU.loop.loopend
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#define LOOP_IN_PROGRESS CPU.loop.loop_in_progress
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#define LOOPCNT CPU.loop.loop_counter
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/* 32 GP registers plus PC. */
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#define NUM_REGS 33
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#endif /* PRU_H */
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