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c75ef631bd
gas/ 2010-02-11 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c: Update copyright. opcodes/ 2010-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Update copyright. * i386-gen.c: Likewise. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise.
663 lines
17 KiB
C
663 lines
17 KiB
C
/* Declarations for Intel 80386 opcode table
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Copyright 2007, 2008, 2009, 2010
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Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "opcode/i386.h"
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#ifdef HAVE_LIMITS_H
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#include <limits.h>
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#endif
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#ifndef CHAR_BIT
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#define CHAR_BIT 8
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#endif
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/* Position of cpu flags bitfiled. */
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enum
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{
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/* i186 or better required */
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Cpu186 = 0,
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/* i286 or better required */
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Cpu286,
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/* i386 or better required */
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Cpu386,
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/* i486 or better required */
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Cpu486,
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/* i585 or better required */
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Cpu586,
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/* i686 or better required */
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Cpu686,
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/* CLFLUSH Instuction support required */
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CpuClflush,
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/* SYSCALL Instuctions support required */
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CpuSYSCALL,
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/* Floating point support required */
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Cpu8087,
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/* i287 support required */
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Cpu287,
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/* i387 support required */
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Cpu387,
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/* i686 and floating point support required */
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Cpu687,
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/* SSE3 and floating point support required */
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CpuFISTTP,
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/* MMX support required */
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CpuMMX,
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/* SSE support required */
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CpuSSE,
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/* SSE2 support required */
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CpuSSE2,
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/* 3dnow! support required */
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Cpu3dnow,
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/* 3dnow! Extensions support required */
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Cpu3dnowA,
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/* SSE3 support required */
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CpuSSE3,
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/* VIA PadLock required */
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CpuPadLock,
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/* AMD Secure Virtual Machine Ext-s required */
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CpuSVME,
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/* VMX Instructions required */
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CpuVMX,
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/* SMX Instructions required */
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CpuSMX,
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/* SSSE3 support required */
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CpuSSSE3,
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/* SSE4a support required */
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CpuSSE4a,
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/* ABM New Instructions required */
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CpuABM,
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/* SSE4.1 support required */
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CpuSSE4_1,
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/* SSE4.2 support required */
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CpuSSE4_2,
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/* AVX support required */
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CpuAVX,
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/* Intel L1OM support required */
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CpuL1OM,
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/* Xsave/xrstor New Instuctions support required */
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CpuXsave,
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/* AES support required */
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CpuAES,
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/* PCLMUL support required */
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CpuPCLMUL,
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/* FMA support required */
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CpuFMA,
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/* FMA4 support required */
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CpuFMA4,
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/* XOP support required */
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CpuXOP,
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/* LWP support required */
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CpuLWP,
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/* MOVBE Instuction support required */
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CpuMovbe,
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/* EPT Instructions required */
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CpuEPT,
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/* RDTSCP Instuction support required */
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CpuRdtscp,
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/* 64bit support available, used by -march= in assembler. */
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CpuLM,
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/* 64bit support required */
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Cpu64,
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/* Not supported in the 64bit mode */
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CpuNo64,
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/* The last bitfield in i386_cpu_flags. */
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CpuMax = CpuNo64
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};
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#define CpuNumOfUints \
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(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
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#define CpuNumOfBits \
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(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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/* If you get a compiler error for zero width of the unused field,
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comment it out. */
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#define CpuUnused (CpuMax + 1)
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/* We can check if an instruction is available with array instead
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of bitfield. */
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typedef union i386_cpu_flags
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{
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struct
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{
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unsigned int cpui186:1;
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unsigned int cpui286:1;
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unsigned int cpui386:1;
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unsigned int cpui486:1;
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unsigned int cpui586:1;
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unsigned int cpui686:1;
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unsigned int cpuclflush:1;
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unsigned int cpusyscall:1;
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unsigned int cpu8087:1;
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unsigned int cpu287:1;
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unsigned int cpu387:1;
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unsigned int cpu687:1;
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unsigned int cpufisttp:1;
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unsigned int cpummx:1;
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unsigned int cpusse:1;
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unsigned int cpusse2:1;
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unsigned int cpua3dnow:1;
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unsigned int cpua3dnowa:1;
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unsigned int cpusse3:1;
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unsigned int cpupadlock:1;
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unsigned int cpusvme:1;
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unsigned int cpuvmx:1;
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unsigned int cpusmx:1;
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unsigned int cpussse3:1;
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unsigned int cpusse4a:1;
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unsigned int cpuabm:1;
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unsigned int cpusse4_1:1;
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unsigned int cpusse4_2:1;
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unsigned int cpuavx:1;
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unsigned int cpul1om:1;
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unsigned int cpuxsave:1;
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unsigned int cpuaes:1;
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unsigned int cpupclmul:1;
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unsigned int cpufma:1;
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unsigned int cpufma4:1;
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unsigned int cpuxop:1;
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unsigned int cpulwp:1;
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unsigned int cpumovbe:1;
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unsigned int cpuept:1;
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unsigned int cpurdtscp:1;
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unsigned int cpulm:1;
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unsigned int cpu64:1;
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unsigned int cpuno64:1;
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#ifdef CpuUnused
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unsigned int unused:(CpuNumOfBits - CpuUnused);
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#endif
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} bitfield;
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unsigned int array[CpuNumOfUints];
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} i386_cpu_flags;
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/* Position of opcode_modifier bits. */
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enum
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{
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/* has direction bit. */
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D = 0,
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/* set if operands can be words or dwords encoded the canonical way */
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W,
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/* Skip the current insn and use the next insn in i386-opc.tbl to swap
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operand in encoding. */
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S,
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/* insn has a modrm byte. */
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Modrm,
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/* register is in low 3 bits of opcode */
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ShortForm,
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/* special case for jump insns. */
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Jump,
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/* call and jump */
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JumpDword,
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/* loop and jecxz */
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JumpByte,
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/* special case for intersegment leaps/calls */
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JumpInterSegment,
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/* FP insn memory format bit, sized by 0x4 */
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FloatMF,
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/* src/dest swap for floats. */
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FloatR,
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/* has float insn direction bit. */
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FloatD,
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/* needs size prefix if in 32-bit mode */
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Size16,
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/* needs size prefix if in 16-bit mode */
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Size32,
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/* needs size prefix if in 64-bit mode */
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Size64,
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/* instruction ignores operand size prefix and in Intel mode ignores
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mnemonic size suffix check. */
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IgnoreSize,
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/* default insn size depends on mode */
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DefaultSize,
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/* b suffix on instruction illegal */
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No_bSuf,
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/* w suffix on instruction illegal */
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No_wSuf,
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/* l suffix on instruction illegal */
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No_lSuf,
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/* s suffix on instruction illegal */
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No_sSuf,
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/* q suffix on instruction illegal */
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No_qSuf,
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/* long double suffix on instruction illegal */
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No_ldSuf,
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/* instruction needs FWAIT */
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FWait,
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/* quick test for string instructions */
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IsString,
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/* quick test for lockable instructions */
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IsLockable,
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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RegKludge,
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/* The first operand must be xmm0 */
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FirstXmm0,
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/* An implicit xmm0 as the first operand */
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Implicit1stXmm0,
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/* Convert to DWORD */
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ToDword,
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/* Convert to QWORD */
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ToQword,
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/* Address prefix changes operand 0 */
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AddrPrefixOp0,
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/* opcode is a prefix */
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IsPrefix,
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/* instruction has extension in 8 bit imm */
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ImmExt,
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/* instruction don't need Rex64 prefix. */
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NoRex64,
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/* instruction require Rex64 prefix. */
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Rex64,
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/* deprecated fp insn, gets a warning */
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Ugh,
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/* insn has VEX prefix:
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1: 128bit VEX prefix.
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2: 256bit VEX prefix.
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3: Scalar VEX prefix.
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*/
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#define VEX128 1
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#define VEX256 2
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#define VEXScalar 3
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Vex,
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/* How to encode VEX.vvvv:
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0: VEX.vvvv must be 1111b.
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1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
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the content of source registers will be preserved.
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VEX.DDS. The second register operand is encoded in VEX.vvvv
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where the content of first source register will be overwritten
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by the result.
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For assembler, there are no difference between VEX.NDS and
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VEX.DDS.
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2. VEX.NDD. Register destination is encoded in VEX.vvvv.
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3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
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of the operands can access a memory location.
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*/
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#define VEXXDS 1
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#define VEXNDD 2
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#define VEXLWP 3
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VexVVVV,
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/* How the VEX.W bit is used:
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0: Set by the REX.W bit.
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1: VEX.W0. Should always be 0.
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2: VEX.W1. Should always be 1.
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*/
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#define VEXW0 1
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#define VEXW1 2
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VexW,
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/* VEX opcode prefix:
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0: VEX 0x0F opcode prefix.
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1: VEX 0x0F38 opcode prefix.
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2: VEX 0x0F3A opcode prefix
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3: XOP 0x08 opcode prefix.
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4: XOP 0x09 opcode prefix
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5: XOP 0x0A opcode prefix.
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*/
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#define VEX0F 0
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#define VEX0F38 1
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#define VEX0F3A 2
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#define XOP08 3
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#define XOP09 4
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#define XOP0A 5
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VexOpcode,
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/* number of VEX source operands:
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0: <= 2 source operands.
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1: 2 XOP source operands.
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2: 3 source operands.
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*/
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#define XOP2SOURCES 1
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#define VEX3SOURCES 2
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VexSources,
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/* instruction has VEX 8 bit imm */
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VexImmExt,
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/* SSE to AVX support required */
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SSE2AVX,
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/* No AVX equivalent */
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NoAVX,
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/* Compatible with old (<= 2.8.1) versions of gcc */
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OldGcc,
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/* AT&T mnemonic. */
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ATTMnemonic,
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/* AT&T syntax. */
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ATTSyntax,
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/* Intel syntax. */
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IntelSyntax,
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/* The last bitfield in i386_opcode_modifier. */
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Opcode_Modifier_Max
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};
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typedef struct i386_opcode_modifier
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{
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unsigned int d:1;
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unsigned int w:1;
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unsigned int s:1;
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unsigned int modrm:1;
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unsigned int shortform:1;
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unsigned int jump:1;
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unsigned int jumpdword:1;
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unsigned int jumpbyte:1;
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unsigned int jumpintersegment:1;
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unsigned int floatmf:1;
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unsigned int floatr:1;
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unsigned int floatd:1;
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unsigned int size16:1;
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unsigned int size32:1;
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unsigned int size64:1;
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unsigned int ignoresize:1;
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unsigned int defaultsize:1;
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unsigned int no_bsuf:1;
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unsigned int no_wsuf:1;
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unsigned int no_lsuf:1;
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unsigned int no_ssuf:1;
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unsigned int no_qsuf:1;
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unsigned int no_ldsuf:1;
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unsigned int fwait:1;
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unsigned int isstring:1;
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unsigned int islockable:1;
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unsigned int regkludge:1;
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unsigned int firstxmm0:1;
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unsigned int implicit1stxmm0:1;
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unsigned int todword:1;
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unsigned int toqword:1;
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unsigned int addrprefixop0:1;
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unsigned int isprefix:1;
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unsigned int immext:1;
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unsigned int norex64:1;
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unsigned int rex64:1;
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unsigned int ugh:1;
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unsigned int vex:2;
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unsigned int vexvvvv:2;
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unsigned int vexw:2;
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unsigned int vexopcode:3;
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unsigned int vexsources:2;
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unsigned int veximmext:1;
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unsigned int sse2avx:1;
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unsigned int noavx:1;
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unsigned int oldgcc:1;
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unsigned int attmnemonic:1;
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unsigned int attsyntax:1;
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unsigned int intelsyntax:1;
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} i386_opcode_modifier;
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/* Position of operand_type bits. */
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enum
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{
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/* 8bit register */
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Reg8 = 0,
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/* 16bit register */
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Reg16,
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/* 32bit register */
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Reg32,
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/* 64bit register */
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Reg64,
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/* Floating pointer stack register */
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FloatReg,
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/* MMX register */
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RegMMX,
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/* SSE register */
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RegXMM,
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/* AVX registers */
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RegYMM,
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/* Control register */
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Control,
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/* Debug register */
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Debug,
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/* Test register */
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Test,
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/* 2 bit segment register */
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SReg2,
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/* 3 bit segment register */
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SReg3,
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/* 1 bit immediate */
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Imm1,
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/* 8 bit immediate */
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Imm8,
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/* 8 bit immediate sign extended */
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Imm8S,
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/* 16 bit immediate */
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Imm16,
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/* 32 bit immediate */
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Imm32,
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/* 32 bit immediate sign extended */
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Imm32S,
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/* 64 bit immediate */
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Imm64,
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/* 8bit/16bit/32bit displacements are used in different ways,
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depending on the instruction. For jumps, they specify the
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size of the PC relative displacement, for instructions with
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memory operand, they specify the size of the offset relative
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to the base register, and for instructions with memory offset
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such as `mov 1234,%al' they specify the size of the offset
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relative to the segment base. */
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/* 8 bit displacement */
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Disp8,
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/* 16 bit displacement */
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Disp16,
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/* 32 bit displacement */
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Disp32,
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/* 32 bit signed displacement */
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Disp32S,
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/* 64 bit displacement */
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Disp64,
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/* Accumulator %al/%ax/%eax/%rax */
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Acc,
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/* Floating pointer top stack register %st(0) */
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FloatAcc,
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/* Register which can be used for base or index in memory operand. */
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BaseIndex,
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/* Register to hold in/out port addr = dx */
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InOutPortReg,
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/* Register to hold shift count = cl */
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ShiftCount,
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/* Absolute address for jump. */
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JumpAbsolute,
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/* String insn operand with fixed es segment */
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EsSeg,
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/* RegMem is for instructions with a modrm byte where the register
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destination operand should be encoded in the mod and regmem fields.
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Normally, it will be encoded in the reg field. We add a RegMem
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flag to the destination register operand to indicate that it should
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be encoded in the regmem field. */
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RegMem,
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/* Memory. */
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Mem,
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/* BYTE memory. */
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Byte,
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/* WORD memory. 2 byte */
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Word,
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/* DWORD memory. 4 byte */
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Dword,
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/* FWORD memory. 6 byte */
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Fword,
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/* QWORD memory. 8 byte */
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Qword,
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/* TBYTE memory. 10 byte */
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Tbyte,
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/* XMMWORD memory. */
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Xmmword,
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/* YMMWORD memory. */
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Ymmword,
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/* Unspecified memory size. */
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Unspecified,
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/* Any memory size. */
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Anysize,
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/* Vector 4 bit immediate. */
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Vec_Imm4,
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/* The last bitfield in i386_operand_type. */
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OTMax
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};
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#define OTNumOfUints \
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(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
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#define OTNumOfBits \
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(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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/* If you get a compiler error for zero width of the unused field,
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comment it out. */
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#define OTUnused (OTMax + 1)
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typedef union i386_operand_type
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{
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struct
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{
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unsigned int reg8:1;
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unsigned int reg16:1;
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unsigned int reg32:1;
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unsigned int reg64:1;
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unsigned int floatreg:1;
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unsigned int regmmx:1;
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unsigned int regxmm:1;
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unsigned int regymm:1;
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unsigned int control:1;
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unsigned int debug:1;
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unsigned int test:1;
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unsigned int sreg2:1;
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unsigned int sreg3:1;
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unsigned int imm1:1;
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unsigned int imm8:1;
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unsigned int imm8s:1;
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unsigned int imm16:1;
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unsigned int imm32:1;
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unsigned int imm32s:1;
|
|
unsigned int imm64:1;
|
|
unsigned int disp8:1;
|
|
unsigned int disp16:1;
|
|
unsigned int disp32:1;
|
|
unsigned int disp32s:1;
|
|
unsigned int disp64:1;
|
|
unsigned int acc:1;
|
|
unsigned int floatacc:1;
|
|
unsigned int baseindex:1;
|
|
unsigned int inoutportreg:1;
|
|
unsigned int shiftcount:1;
|
|
unsigned int jumpabsolute:1;
|
|
unsigned int esseg:1;
|
|
unsigned int regmem:1;
|
|
unsigned int mem:1;
|
|
unsigned int byte:1;
|
|
unsigned int word:1;
|
|
unsigned int dword:1;
|
|
unsigned int fword:1;
|
|
unsigned int qword:1;
|
|
unsigned int tbyte:1;
|
|
unsigned int xmmword:1;
|
|
unsigned int ymmword:1;
|
|
unsigned int unspecified:1;
|
|
unsigned int anysize:1;
|
|
unsigned int vec_imm4:1;
|
|
#ifdef OTUnused
|
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
|
#endif
|
|
} bitfield;
|
|
unsigned int array[OTNumOfUints];
|
|
} i386_operand_type;
|
|
|
|
typedef struct insn_template
|
|
{
|
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
|
char *name;
|
|
|
|
/* how many operands */
|
|
unsigned int operands;
|
|
|
|
/* base_opcode is the fundamental opcode byte without optional
|
|
prefix(es). */
|
|
unsigned int base_opcode;
|
|
#define Opcode_D 0x2 /* Direction bit:
|
|
set if Reg --> Regmem;
|
|
unset if Regmem --> Reg. */
|
|
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
|
|
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
|
|
|
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
|
This field is also used to store the 8-bit opcode suffix for the
|
|
AMD 3DNow! instructions.
|
|
If this template has no extension opcode (the usual case) use None
|
|
Instructions */
|
|
unsigned int extension_opcode;
|
|
#define None 0xffff /* If no extension_opcode is possible. */
|
|
|
|
/* Opcode length. */
|
|
unsigned char opcode_length;
|
|
|
|
/* cpu feature flags */
|
|
i386_cpu_flags cpu_flags;
|
|
|
|
/* the bits in opcode_modifier are used to generate the final opcode from
|
|
the base_opcode. These bits also are used to detect alternate forms of
|
|
the same instruction */
|
|
i386_opcode_modifier opcode_modifier;
|
|
|
|
/* operand_types[i] describes the type of operand i. This is made
|
|
by OR'ing together all of the possible type masks. (e.g.
|
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
|
either a register or an immediate operand. */
|
|
i386_operand_type operand_types[MAX_OPERANDS];
|
|
}
|
|
insn_template;
|
|
|
|
extern const insn_template i386_optab[];
|
|
|
|
/* these are for register name --> number & type hash lookup */
|
|
typedef struct
|
|
{
|
|
char *reg_name;
|
|
i386_operand_type reg_type;
|
|
unsigned char reg_flags;
|
|
#define RegRex 0x1 /* Extended register. */
|
|
#define RegRex64 0x2 /* Extended 8 bit register. */
|
|
unsigned char reg_num;
|
|
#define RegRip ((unsigned char ) ~0)
|
|
#define RegEip (RegRip - 1)
|
|
/* EIZ and RIZ are fake index registers. */
|
|
#define RegEiz (RegEip - 1)
|
|
#define RegRiz (RegEiz - 1)
|
|
/* FLAT is a fake segment register (Intel mode). */
|
|
#define RegFlat ((unsigned char) ~0)
|
|
signed char dw2_regnum[2];
|
|
#define Dw2Inval (-1)
|
|
}
|
|
reg_entry;
|
|
|
|
/* Entries in i386_regtab. */
|
|
#define REGNAM_AL 1
|
|
#define REGNAM_AX 25
|
|
#define REGNAM_EAX 41
|
|
|
|
extern const reg_entry i386_regtab[];
|
|
extern const unsigned int i386_regtab_size;
|
|
|
|
typedef struct
|
|
{
|
|
char *seg_name;
|
|
unsigned int seg_prefix;
|
|
}
|
|
seg_entry;
|
|
|
|
extern const seg_entry cs;
|
|
extern const seg_entry ds;
|
|
extern const seg_entry ss;
|
|
extern const seg_entry es;
|
|
extern const seg_entry fs;
|
|
extern const seg_entry gs;
|