mirror of
https://sourceware.org/git/binutils-gdb.git
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3cc17af589
Now that the opcode table gets preprocessed, undo parts of commit
dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the
preprocessor handle the expansion there, while making the expansions
explicit in i386-gen and the register table.
322 lines
13 KiB
Plaintext
322 lines
13 KiB
Plaintext
// i386 register table.
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// Copyright (C) 2007-2019 Free Software Foundation, Inc.
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//
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// This file is part of the GNU opcodes library.
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//
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// This library is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3, or (at your option)
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// any later version.
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//
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// It is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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// License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with GAS; see the file COPYING. If not, write to the Free
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// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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// 02110-1301, USA.
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// Make %st first as we test for it.
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st, Reg|Acc|Tbyte, 0, 0, 11, 33
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// 8 bit regs
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al, Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
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cl, Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
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dl, Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
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bl, Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
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ah, Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
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ch, Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
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dh, Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
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bh, Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
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axl, Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
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cxl, Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
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dxl, Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
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bxl, Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
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spl, Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
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bpl, Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
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sil, Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
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dil, Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
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r8b, Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
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r9b, Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
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r10b, Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
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r11b, Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
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r12b, Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
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r13b, Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
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r14b, Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
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r15b, Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
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// 16 bit regs
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ax, Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
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cx, Reg|Word, 0, 1, Dw2Inval, Dw2Inval
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dx, Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
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bx, Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
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sp, Reg|Word, 0, 4, Dw2Inval, Dw2Inval
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bp, Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
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si, Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
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di, Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
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r8w, Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
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r9w, Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
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r10w, Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
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r11w, Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
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r12w, Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
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r13w, Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
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r14w, Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
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r15w, Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
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// 32 bit regs
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eax, Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
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ecx, Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
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edx, Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
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ebx, Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
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esp, Reg|Dword, 0, 4, 4, Dw2Inval
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ebp, Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
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esi, Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
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edi, Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
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r8d, Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
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r9d, Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
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r10d, Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
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r11d, Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
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r12d, Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
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r13d, Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
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r14d, Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
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r15d, Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
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rax, Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
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rcx, Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
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rdx, Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
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rbx, Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
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rsp, Reg|Qword, 0, 4, Dw2Inval, 7
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rbp, Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
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rsi, Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
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rdi, Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
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r8, Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
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r9, Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
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r10, Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
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r11, Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
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r12, Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
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r13, Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
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r14, Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
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r15, Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
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// Vector mask registers.
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k0, RegMask, 0, 0, 93, 118
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k1, RegMask, 0, 1, 94, 119
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k2, RegMask, 0, 2, 95, 120
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k3, RegMask, 0, 3, 96, 121
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k4, RegMask, 0, 4, 97, 122
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k5, RegMask, 0, 5, 98, 123
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k6, RegMask, 0, 6, 99, 124
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k7, RegMask, 0, 7, 100, 125
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// Segment registers.
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es, SReg, 0, 0, 40, 50
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cs, SReg, 0, 1, 41, 51
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ss, SReg, 0, 2, 42, 52
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ds, SReg, 0, 3, 43, 53
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fs, SReg, 0, 4, 44, 54
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gs, SReg, 0, 5, 45, 55
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flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
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// Control registers.
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cr0, Control, 0, 0, Dw2Inval, Dw2Inval
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cr1, Control, 0, 1, Dw2Inval, Dw2Inval
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cr2, Control, 0, 2, Dw2Inval, Dw2Inval
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cr3, Control, 0, 3, Dw2Inval, Dw2Inval
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cr4, Control, 0, 4, Dw2Inval, Dw2Inval
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cr5, Control, 0, 5, Dw2Inval, Dw2Inval
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cr6, Control, 0, 6, Dw2Inval, Dw2Inval
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cr7, Control, 0, 7, Dw2Inval, Dw2Inval
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cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
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cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
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cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
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cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
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cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
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cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
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cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
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cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
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// Debug registers.
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db0, Debug, 0, 0, Dw2Inval, Dw2Inval
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db1, Debug, 0, 1, Dw2Inval, Dw2Inval
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db2, Debug, 0, 2, Dw2Inval, Dw2Inval
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db3, Debug, 0, 3, Dw2Inval, Dw2Inval
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db4, Debug, 0, 4, Dw2Inval, Dw2Inval
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db5, Debug, 0, 5, Dw2Inval, Dw2Inval
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db6, Debug, 0, 6, Dw2Inval, Dw2Inval
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db7, Debug, 0, 7, Dw2Inval, Dw2Inval
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db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
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dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
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dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
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dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
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dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
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dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
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dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
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dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
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dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
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dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
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dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
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dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
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dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
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dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
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dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
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dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
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// Test registers.
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tr0, Test, 0, 0, Dw2Inval, Dw2Inval
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tr1, Test, 0, 1, Dw2Inval, Dw2Inval
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tr2, Test, 0, 2, Dw2Inval, Dw2Inval
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tr3, Test, 0, 3, Dw2Inval, Dw2Inval
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tr4, Test, 0, 4, Dw2Inval, Dw2Inval
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tr5, Test, 0, 5, Dw2Inval, Dw2Inval
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tr6, Test, 0, 6, Dw2Inval, Dw2Inval
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tr7, Test, 0, 7, Dw2Inval, Dw2Inval
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// MMX and simd registers.
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mm0, RegMMX, 0, 0, 29, 41
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mm1, RegMMX, 0, 1, 30, 42
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mm2, RegMMX, 0, 2, 31, 43
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mm3, RegMMX, 0, 3, 32, 44
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mm4, RegMMX, 0, 4, 33, 45
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mm5, RegMMX, 0, 5, 34, 46
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mm6, RegMMX, 0, 6, 35, 47
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mm7, RegMMX, 0, 7, 36, 48
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xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17
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xmm1, RegSIMD|Xmmword, 0, 1, 22, 18
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xmm2, RegSIMD|Xmmword, 0, 2, 23, 19
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xmm3, RegSIMD|Xmmword, 0, 3, 24, 20
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xmm4, RegSIMD|Xmmword, 0, 4, 25, 21
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xmm5, RegSIMD|Xmmword, 0, 5, 26, 22
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xmm6, RegSIMD|Xmmword, 0, 6, 27, 23
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xmm7, RegSIMD|Xmmword, 0, 7, 28, 24
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xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
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xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
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xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
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xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
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xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
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xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
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xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
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xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
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xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
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xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
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xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
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xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
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xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
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xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
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xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
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xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
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xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
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xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
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xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
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xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
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xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
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xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
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xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
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xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
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// AVX registers.
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ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
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ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
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ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
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ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
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ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
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ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
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ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
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ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
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ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
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ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
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ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
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ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
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ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
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ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
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ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
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ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
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ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
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ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
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ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
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ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
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ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
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ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
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ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
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ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
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ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
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ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
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ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
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ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
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ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
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ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
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ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
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ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
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// AVX512 registers.
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zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
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zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
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zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
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zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
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zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
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zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
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zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
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zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
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zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
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zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
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zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
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zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
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zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
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zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
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zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
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zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
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zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
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zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
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zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
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zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
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zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
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zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
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zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
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zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
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zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
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zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
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zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
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zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
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zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
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zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
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zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
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zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
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// Bound registers for MPX
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bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
|
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
|
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
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|
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
|
|
// No Reg will make these registers rejected for all purposes except
|
|
// for addressing. This saves creating one extra type for RIP/EIP.
|
|
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
|
|
eip, Dword, RegRex64, RegIP, 8, Dw2Inval
|
|
// No Reg will make these registers rejected for all purposes except
|
|
// for addressing.
|
|
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
|
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eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
|
|
// fp regs.
|
|
st(0), Reg|Acc|Tbyte, 0, 0, 11, 33
|
|
st(1), Reg|Tbyte, 0, 1, 12, 34
|
|
st(2), Reg|Tbyte, 0, 2, 13, 35
|
|
st(3), Reg|Tbyte, 0, 3, 14, 36
|
|
st(4), Reg|Tbyte, 0, 4, 15, 37
|
|
st(5), Reg|Tbyte, 0, 5, 16, 38
|
|
st(6), Reg|Tbyte, 0, 6, 17, 39
|
|
st(7), Reg|Tbyte, 0, 7, 18, 40
|
|
// Pseudo-register names only used in .cfi_* directives
|
|
eflags, 0, 0, 0, 9, 49
|
|
rflags, 0, 0, 0, Dw2Inval, 49
|
|
fs.base, 0, 0, 0, Dw2Inval, 58
|
|
gs.base, 0, 0, 0, Dw2Inval, 59
|
|
tr, 0, 0, 0, 48, 62
|
|
ldtr, 0, 0, 0, 49, 63
|
|
// st0...7 for backward compatibility
|
|
st0, 0, 0, 0, 11, 33
|
|
st1, 0, 0, 1, 12, 34
|
|
st2, 0, 0, 2, 13, 35
|
|
st3, 0, 0, 3, 14, 36
|
|
st4, 0, 0, 4, 15, 37
|
|
st5, 0, 0, 5, 16, 38
|
|
st6, 0, 0, 6, 17, 39
|
|
st7, 0, 0, 7, 18, 40
|
|
fcw, 0, 0, 0, 37, 65
|
|
fsw, 0, 0, 0, 38, 66
|
|
mxcsr, 0, 0, 0, 39, 64
|