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b4e87f2c1e
We currently use a padding NOP after a Thumb to Arm interworking veneer (BX pc). The NOP is never executed but may result in a performance penalty on some cores. For this reason this patch changes the NOPs after Thumb to Arm veneers into B .-2 and adds a note to this in the source code for future reference. bfd/ChangeLog: * elf32-arm.c (elf32_thumb2_plt_entry, elf32_arm_plt_thumb_stub, elf32_arm_stub_long_branch_v4t_thumb_thumb, elf32_arm_stub_long_branch_v4t_thumb_arm, elf32_arm_stub_short_branch_v4t_thumb_arm, elf32_arm_stub_long_branch_v4t_thumb_arm_pic, elf32_arm_stub_long_branch_v4t_thumb_thumb_pic, elf32_arm_stub_long_branch_v4t_thumb_tls_pic): Change nop to branch to previous instruction. ld/ChangeLog: * testsuite/ld-arm/cortex-a8-fix-b-plt.d: Update Testcase. * testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d: Likewise. * testsuite/ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. * testsuite/ld-arm/farcall-cond-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-mixed-app.d: Likewise. * testsuite/ld-arm/farcall-mixed-app2.d: Likewise. * testsuite/ld-arm/farcall-mixed-lib-v4t.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * testsuite/ld-arm/farcall-thumb-arm.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * testsuite/ld-arm/fix-arm1176-on.d: Likewise. * testsuite/ld-arm/ifunc-10.dd: Likewise. * testsuite/ld-arm/ifunc-2.dd: Likewise. * testsuite/ld-arm/ifunc-4.dd: Likewise. * testsuite/ld-arm/ifunc-6.dd: Likewise. * testsuite/ld-arm/ifunc-8.dd: Likewise. * testsuite/ld-arm/jump-reloc-veneers-long.d: Likewise. * testsuite/ld-arm/mixed-app.d: Likewise. * testsuite/ld-arm/thumb2-b-interwork.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise. * testsuite/ld-arm/tls-thumb1.d: Likewise.
32 lines
858 B
Makefile
32 lines
858 B
Makefile
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.*
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Disassembly of section \.plt:
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00008000 <.*>:
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8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
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8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
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8008: e08fe00e add lr, pc, lr
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800c: e5bef008 ldr pc, \[lr, #8\]!
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8010: 00000ffc \.word 0x00000ffc
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00008014 <bar@plt>:
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8014: 4778 bx pc
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8016: e7fd b.n .+ <.+>
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8018: e28fc600 add ip, pc, #0, 12
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801c: e28cca00 add ip, ip, #0, 20
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8020: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8
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Disassembly of section \.text:
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00008ff0 <foo>:
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8ff0: 46c0 nop ; \(mov r8, r8\)
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8ff2: f240 0000 movw r0, #0
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8ff6: f240 0000 movw r0, #0
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8ffa: f240 0000 movw r0, #0
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8ffe: f000 b803 b\.w 9008 <foo\+0x18>
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9002: 0000 movs r0, r0
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9004: 0000 movs r0, r0
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9006: 0000 movs r0, r0
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9008: f7ff b804 b\.w 8014 <bar@plt>
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