binutils-gdb/opcodes
Nelson Chu f786c359c1 RISC-V: Dump objects according to the elf architecture attribute.
For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string.  This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed.  Consider the following case,

nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add     a0, a0, a0
.byte   0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    nop
   8:   00000013                nop
   c:   00000013                nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
  Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"

The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong.  After
applying this patch, I get the following result,

nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o

temp.o:     file format elf32-littleriscv

Disassembly of section .text:

00000000 <.text>:
   0:   00a50533                add     a0,a0,a0
   4:   01                      .byte   0x01
   5:   00                      .byte   0x00
   6:   0001                    .2byte  0x1
   8:   00000013                nop
   c:   00000013                nop

For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions.  Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.

However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes.  We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized.  Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.

This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains.  Also, tested by --enable-targets=all and can build
riscv-gdb successfully.

bfd/
	* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
	codes for riscv_parse_subset_t setting.
	* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
	(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	* elfxx-riscv.h: Added extern for riscv_subset_supports and
	riscv_multi_subset_supports.
gas/
	* config/tc-riscv.c (riscv_subset_supports): Moved to
	bfd/elfxx-riscv.c.
	(riscv_multi_subset_supports): Likewise.
	(riscv_rps_as): Defined for architectrue parser.
	(riscv_set_arch): Updated.
	(riscv_set_abi_by_arch): Likewise.
	(riscv_csr_address): Likewise.
	(reg_lookup_internal): Likewise.
	(riscv_ip): Likewise.
	(s_riscv_option): Updated.
	* testsuite/gas/riscv/mapping-04b.d: Updated.
	* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
	* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
	* riscv-dis.c: Include elfxx-riscv.h since we need the
	architecture parser.  Also removed the cpu-riscv.h, it
	is already included in elfxx-riscv.h.
	(default_isa_spec): Defined since the parser need this
	to set the default architecture string.
	(xlen): Moved out from riscv_disassemble_insn as a global
	variable, it is more convenient to initialize riscv_rps_dis.
	(riscv_subsets): Defined to recoed the supported
	extensions.
	(riscv_rps_dis): Defined for architectrue parser.
	(riscv_disassemble_insn): Call riscv_multi_subset_supports
	to make sure if the instructions are valid or not.
	(print_insn_riscv): Initialize the riscv_subsets by parsing
	the elf architectrue attribute.  Otherwise, set the default
	architectrue string to rv64gc.
2021-11-11 16:59:13 +08:00
..
po LoongArch opcodes support 2021-10-24 21:36:31 +10:30
.gitignore
aarch64-asm-2.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
aarch64-asm.c arm64: add two initializers 2021-04-19 15:41:35 +02:00
aarch64-asm.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
aarch64-dis-2.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
aarch64-dis.c Missing va_end in aarch64-dis.c 2021-11-05 19:03:34 +10:30
aarch64-dis.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
aarch64-gen.c opcodes: constify aarch64_opcode_tables 2021-07-01 17:51:00 -04:00
aarch64-opc-2.c
aarch64-opc.c aarch64: New instructions for maintenance of GPT entries cached in a TLB 2021-04-19 15:01:56 +01:00
aarch64-opc.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
aarch64-tbl.h opcodes: constify aarch64_opcode_tables 2021-07-01 17:51:00 -04:00
aclocal.m4
alpha-dis.c
alpha-opc.c
arc-dis.c arc: Construct disassembler options dynamically 2021-06-02 15:32:58 +03:00
arc-dis.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
arc-ext-tbl.h
arc-ext.c
arc-ext.h
arc-fxi.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
arc-nps400-tbl.h
arc-opc.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
arc-regs.h opcodes: Fix the auxiliary register numbers for ARC HS 2021-08-17 18:33:05 +02:00
arc-tbl.h
arm-dis.c arm: add armv9-a architecture to -march 2021-11-01 10:51:03 +00:00
avr-dis.c Remove bfd_stdint.h 2021-03-31 10:49:23 +10:30
bfin-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
bpf-asm.c
bpf-desc.c
bpf-desc.h
bpf-dis.c
bpf-ibld.c
bpf-opc.c
bpf-opc.h
cgen-asm.c
cgen-asm.in
cgen-bitset.c
cgen-dis.c opcodes: make use of __builtin_popcount when available 2021-06-22 09:53:13 +01:00
cgen-dis.in
cgen-ibld.in
cgen-opc.c C99 opcodes configury 2021-04-05 15:28:04 +09:30
cgen.sh opcodes: cris: move desc & opc files from sim/ 2021-05-24 18:42:34 -04:00
ChangeLog opcodes: Fix RPATH not being set for dynamic libbfd dependency 2021-10-27 12:21:14 +01:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-2017
ChangeLog-2018
ChangeLog-2019
ChangeLog-2020
ChangeLog-9297
ChangeLog-9899
config.in ENABLE_CHECKING in bfd, opcodes, binutils, ld 2021-04-13 00:35:44 +09:30
configure opcodes: Fix RPATH not being set for dynamic libbfd dependency 2021-10-27 12:21:14 +01:00
configure.ac opcodes: Fix RPATH not being set for dynamic libbfd dependency 2021-10-27 12:21:14 +01:00
configure.com
cr16-dis.c Remove strneq macro and use startswith. 2021-04-01 15:00:56 +02:00
cr16-opc.c
cris-desc.c Regen cris files 2021-05-25 17:17:04 +09:30
cris-desc.h Regen cris files 2021-05-25 17:17:04 +09:30
cris-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
cris-opc.c
cris-opc.h Regen cris files 2021-05-25 17:17:04 +09:30
crx-dis.c
crx-opc.c
csky-dis.c PR28168: [CSKY] Fix stack overflow in disassembler 2021-08-13 14:13:58 +08:00
csky-opc.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
d10v-dis.c
d10v-opc.c opcodes: d10v: simplify header includes 2021-11-02 22:57:52 -04:00
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c Return symbol from symbol_at_address_func 2021-04-06 23:25:09 +09:30
dis-init.c
disassemble.c LoongArch opcodes support 2021-10-24 21:36:31 +10:30
disassemble.h LoongArch opcodes support 2021-10-24 21:36:31 +10:30
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c
frv-opc.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
frv-opc.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
ft32-dis.c FT32: Remove recursion in ft32_opcode 2021-08-24 20:39:29 +09:30
ft32-opc.c
h8300-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
hppa-dis.c
i386-dis-evex-len.h x86/Intel: correct AVX512 S/G disassembly 2021-03-10 08:20:29 +01:00
i386-dis-evex-mod.h x86: drop xmm_m{b,w,d,q}_mode 2021-07-22 13:08:39 +02:00
i386-dis-evex-prefix.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-dis-evex-reg.h x86/Intel: correct AVX512 S/G disassembly 2021-03-10 08:20:29 +01:00
i386-dis-evex-w.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-dis-evex.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-dis.c x86: Print {bad} on invalid broadcast in OP_E_memory 2021-09-28 11:13:50 +08:00
i386-gen.c [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-init.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-opc.c x86: drop seg_entry 2021-03-30 14:09:41 +02:00
i386-opc.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-opc.tbl [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
i386-reg.tbl x86: adjust st(<N>) parsing 2021-03-30 14:08:11 +02:00
i386-tbl.h [PATCH 1/2] Enable Intel AVX512_FP16 instructions 2021-08-05 21:03:41 +08:00
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c Add startswith function and use it instead of CONST_STRNEQ. 2021-03-22 11:01:43 +01:00
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c
lm32-opc.c
lm32-opc.h
lm32-opinst.c
loongarch-coder.c LoongArch opcodes support 2021-10-24 21:36:31 +10:30
loongarch-dis.c LoongArch opcodes support 2021-10-24 21:36:31 +10:30
loongarch-opc.c LoongArch opcodes support 2021-10-24 21:36:31 +10:30
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
m68k-opc.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am opcodes: Fix RPATH not being set for dynamic libbfd dependency 2021-10-27 12:21:14 +01:00
Makefile.in opcodes: Fix RPATH not being set for dynamic libbfd dependency 2021-10-27 12:21:14 +01:00
makefile.vms
mcore-dis.c PR1202, mcore disassembler: wrong address loopt 2021-06-03 13:05:57 +09:30
mcore-opc.h
mep-asm.c opcodes: constify & local meps macros 2021-07-01 18:04:16 -04:00
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c
mep-opc.c
mep-opc.h
metag-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
microblaze-dis.c opcodes: constify & scope microblaze opcodes 2021-07-01 17:55:26 -04:00
microblaze-dis.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
microblaze-opc.h opcodes: constify & scope microblaze opcodes 2021-07-01 17:55:26 -04:00
microblaze-opcm.h
micromips-opc.c MIPS/opcodes: Do not use CP0 register names for control registers 2021-05-29 03:26:32 +02:00
mips16-opc.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
mips-dis.c Correct gs264e bfd_mach in mips_arch_choices. 2021-07-27 09:18:27 +08:00
mips-formats.h Use bool in opcodes 2021-03-31 10:49:23 +10:30
mips-opc.c MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions 2021-05-29 03:26:33 +02:00
mmix-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c
mt-opc.c
mt-opc.h
nds32-asm.c opcodes: cleanup nds32 variables 2021-07-01 18:03:02 -04:00
nds32-asm.h Re: Fix minor NDS32 renaming snafu 2021-07-02 20:48:55 +09:30
nds32-dis.c Re: Fix minor NDS32 renaming snafu 2021-07-02 20:48:55 +09:30
nds32-opc.h
nfp-dis.c Add a sanity check to the init_nfp6000_mecsr_sec() function in the NFP disassembler. 2021-09-06 10:44:29 +01:00
nios2-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h
or1k-asm.c or1k: Implement relocation R_OR1K_GOT_AHI16 for gotha() 2021-05-06 20:51:24 +09:00
or1k-desc.c
or1k-desc.h
or1k-dis.c
or1k-ibld.c
or1k-opc.c
or1k-opc.h
or1k-opinst.c
pdp11-dis.c
pdp11-opc.c
pj-dis.c pj: asan: out of bounds, ubsan: left shift of negative 2021-09-03 11:45:58 +09:30
pj-opc.c
ppc-dis.c PowerPC table driven -Mraw disassembly 2021-05-29 21:06:06 +09:30
ppc-opc.c PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5 2021-09-25 18:21:17 -05:00
pru-dis.c
pru-opc.c
riscv-dis.c RISC-V: Dump objects according to the elf architecture attribute. 2021-11-11 16:59:13 +08:00
riscv-opc.c RISC-V: Support aliases for Zbs instructions 2021-10-07 17:09:28 +08:00
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c
s12z-dis.c s12z/disassembler: call memory_error_func when appropriate 2021-10-11 14:07:03 +01:00
s12z-opc.c
s12z-opc.h
s390-dis.c Add startswith function and use it instead of CONST_STRNEQ. 2021-03-22 11:01:43 +01:00
s390-mkopc.c IBM Z: Implement instruction set extensions 2021-02-15 14:32:17 +01:00
s390-opc.c IBM Z: Remove lpswey parameter 2021-08-04 16:51:50 +02:00
s390-opc.txt IBM Z: Remove lpswey parameter 2021-08-04 16:51:50 +02:00
score7-dis.c Remove strneq macro and use startswith. 2021-04-01 15:00:56 +02:00
score-dis.c Remove strneq macro and use startswith. 2021-04-01 15:00:56 +02:00
score-opc.h
sh-dis.c
sh-opc.h
sparc-dis.c
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h C99 opcodes configury 2021-04-05 15:28:04 +09:30
tic4x-dis.c
tic6x-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
tic30-dis.c Fix another strncpy warning 2021-06-19 11:08:55 +09:30
tic54x-dis.c opcodes: tic54x: namespace exported variables 2021-02-08 18:26:08 -05:00
tic54x-opc.c opcodes: tic54x: namespace exported variables 2021-02-08 18:26:08 -05:00
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c Use bool in opcodes 2021-03-31 10:49:23 +10:30
v850-opc.c Fix the V850 assembler's generation of relocations for the st.b instruction. 2021-09-02 12:16:10 +01:00
vax-dis.c ubsan: vax: pointer overflow 2021-06-19 11:08:56 +09:30
visium-dis.c
visium-opc.c
wasm32-dis.c C99 opcodes configury 2021-04-05 15:28:04 +09:30
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c opcodes: xtensa: support branch visualization 2021-05-01 02:47:30 -07:00
z8k-dis.c
z8k-opc.h
z8kgen.c
z80-dis.c z80/disassembler: call memory_error_func when appropriate 2021-10-11 14:07:03 +01:00