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07f9ddfeba
2015-08-11 Jiong Wang <jiong.wang@arm.com> bfd/ PR ld/18668 * elfnn-aarch64.c (aarch64_type_of_stub): Update destination for calls go through plt stub. (elfNN_aarch64_final_link_relocate): Adjust code logic for CALL26, JUMP26 relocation to support inserting veneer for call to plt stub. ld/testsuite/ * ld-aarch64/farcall-b-gsym.s: New test. * ld-aarch64/farcall-b-plt.s: Likewise. * ld-aarch64/farcall-bl-plt.s: Likewise. * ld-aarch64/farcall-b-gsym.d: New expect file. * ld-aarch64/farcall-b-plt.d: Likewise. * ld-aarch64/farcall-bl-plt.d: Likewise.
39 lines
815 B
Makefile
39 lines
815 B
Makefile
#name: aarch64-farcall-bl-plt
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#source: farcall-bl-plt.s
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#as:
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#ld: -shared
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#objdump: -dr
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#...
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Disassembly of section .plt:
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.* <foo@plt-0x20>:
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.*: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
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.*: 90040090 adrp x16, 8010000 <__foo_veneer\+.*>
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.*: f941f611 ldr x17, \[x16,#1000\]
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.*: 910fa210 add x16, x16, #0x3e8
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.*: d61f0220 br x17
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.*: d503201f nop
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.*: d503201f nop
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.*: d503201f nop
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.* <foo@plt>:
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.*: 90040090 adrp x16, 8010000 <__foo_veneer\+.*>
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.*: f941fa11 ldr x17, \[x16,#1008\]
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.*: 910fc210 add x16, x16, #0x3f0
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.*: d61f0220 br x17
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Disassembly of section .text:
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.* <_start>:
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...
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.*: 94000003 bl 80002c8 <__foo_veneer>
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.*: d65f03c0 ret
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.*: 14000007 b 80002e0 <__foo_veneer\+.*>
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.* <__foo_veneer>:
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.*: 90fc0010 adrp x16, 0 <foo@plt-0x2b0>
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.*: 910ac210 add x16, x16, #0x2b0
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.*: d61f0200 br x16
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...
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