mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
32267d593a
This old port setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them. Also migrate off the sim-specific unsignedXX types.
422 lines
11 KiB
C
422 lines
11 KiB
C
/* Simulation code for the CR16 processor.
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Copyright (C) 2008-2022 Free Software Foundation, Inc.
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Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <stdio.h>
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#include <ctype.h>
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#include <limits.h>
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#include "ansidecl.h"
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#include "sim/callback.h"
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#include "opcode/cr16.h"
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#include "bfd.h"
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_LINE_NUMBER 0x00000004
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#define DEBUG_MEMSIZE 0x00000008
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#define DEBUG_INSTRUCTION 0x00000010
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#define DEBUG_TRAP 0x00000020
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#define DEBUG_MEMORY 0x00000040
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#ifndef DEBUG
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#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
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#endif
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extern int cr16_debug;
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#include "sim/sim.h"
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#include "sim-config.h"
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#include "sim-types.h"
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/* FIXME: CR16 defines */
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typedef uint16_t reg_t;
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typedef uint32_t creg_t;
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struct simops
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{
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char mnemonic[12];
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uint32_t size;
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uint32_t mask;
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uint32_t opcode;
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int format;
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char fname[12];
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void (*func)(SIM_DESC, SIM_CPU *);
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int numops;
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operand_desc operands[4];
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};
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enum _ins_type
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{
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INS_UNKNOWN, /* unknown instruction */
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INS_NO_TYPE_INS,
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INS_ARITH_INS,
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INS_LD_STOR_INS,
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INS_BRANCH_INS,
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INS_ARITH_BYTE_INS,
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INS_SHIFT_INS,
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INS_BRANCH_NEQ_INS,
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INS_STOR_IMM_INS,
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INS_CSTBIT_INS,
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INS_MAX
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};
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extern unsigned long ins_type_counters[ (int)INS_MAX ];
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enum {
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SP_IDX = 15,
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};
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/* Write-back slots */
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union slot_data {
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unsigned_1 _1;
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unsigned_2 _2;
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unsigned_4 _4;
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};
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struct slot {
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void *dest;
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int size;
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union slot_data data;
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union slot_data mask;
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};
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enum {
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NR_SLOTS = 16
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};
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#define SLOT (State.slot)
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#define SLOT_NR (State.slot_nr)
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#define SLOT_PEND_MASK(DEST, MSK, VAL) \
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do \
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{ \
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SLOT[SLOT_NR].dest = &(DEST); \
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SLOT[SLOT_NR].size = sizeof (DEST); \
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switch (sizeof (DEST)) \
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{ \
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case 1: \
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SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
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SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
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break; \
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case 2: \
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SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
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SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
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break; \
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case 4: \
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SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
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SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
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break; \
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} \
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SLOT_NR = (SLOT_NR + 1); \
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} \
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while (0)
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#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
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#define SLOT_DISCARD() (SLOT_NR = 0)
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#define SLOT_FLUSH() \
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do \
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{ \
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int i; \
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for (i = 0; i < SLOT_NR; i++) \
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{ \
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switch (SLOT[i].size) \
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{ \
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case 1: \
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*(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
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*(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
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break; \
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case 2: \
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*(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
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*(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
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break; \
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case 4: \
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*(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
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*(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
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break; \
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} \
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} \
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SLOT_NR = 0; \
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} \
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while (0)
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#define SLOT_DUMP() \
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do \
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{ \
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int i; \
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for (i = 0; i < SLOT_NR; i++) \
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{ \
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switch (SLOT[i].size) \
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{ \
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case 1: \
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printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._1, \
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(unsigned) SLOT[i].data._1); \
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break; \
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case 2: \
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printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._2, \
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(unsigned) SLOT[i].data._2); \
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break; \
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case 4: \
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printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._4, \
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(unsigned) SLOT[i].data._4); \
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break; \
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case 8: \
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printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) (SLOT[i].mask._8 >> 32), \
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(unsigned) SLOT[i].mask._8, \
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(unsigned) (SLOT[i].data._8 >> 32), \
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(unsigned) SLOT[i].data._8); \
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break; \
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} \
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} \
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} \
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while (0)
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struct _state
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{
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creg_t regs[16]; /* general-purpose registers */
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#define GPR(N) (State.regs[(N)] + 0)
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#define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
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#define GPR32(N) \
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(N < 12) ? \
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((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \
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: GPR (N)
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#define SET_GPR32(N,VAL) do { \
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if (N < 11) \
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{ SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
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else { if ( N == 11) \
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{ SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
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SET_GPR (N, ((VAL) & 0xffff));} \
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else SET_GPR (N, (VAL));} \
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} while (0)
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creg_t cregs[16]; /* control registers */
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#define CREG(N) (State.cregs[(N)] + 0)
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#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
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#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
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reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
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#define HELD_SP(N) (State.sp[(N)] + 0)
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#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
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/* writeback info */
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struct slot slot[NR_SLOTS];
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int slot_nr;
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/* trace data */
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struct {
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uint16_t psw;
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} trace;
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int pc_changed;
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/* NOTE: everything below this line is not reset by
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sim_create_inferior() */
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enum _ins_type ins_type;
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};
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extern struct _state State;
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extern uint32_t OP[4];
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extern uint32_t sign_flag;
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extern struct simops Simops[];
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enum
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{
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PC_CR = 0,
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BDS_CR = 1,
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BSR_CR = 2,
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DCR_CR = 3,
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CAR0_CR = 5,
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CAR1_CR = 7,
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CFG_CR = 9,
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PSR_CR = 10,
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INTBASE_CR = 11,
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ISP_CR = 13,
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USP_CR = 15
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};
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enum
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{
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PSR_I_BIT = 0x0800,
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PSR_P_BIT = 0x0400,
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PSR_E_BIT = 0x0200,
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PSR_N_BIT = 0x0080,
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PSR_Z_BIT = 0x0040,
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PSR_F_BIT = 0x0020,
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PSR_U_BIT = 0x0008,
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PSR_L_BIT = 0x0004,
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PSR_T_BIT = 0x0002,
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PSR_C_BIT = 0x0001
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};
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#define PSR CREG (PSR_CR)
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#define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
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#define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
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#define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
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#define PSR_SM ((PSR & PSR_SM_BIT) != 0)
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#define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
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#define PSR_I ((PSR & PSR_I_BIT) != 0)
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#define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
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#define PSR_DB ((PSR & PSR_DB_BIT) != 0)
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#define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
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#define PSR_P ((PSR & PSR_P_BIT) != 0)
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#define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
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#define PSR_E ((PSR & PSR_E_BIT) != 0)
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#define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
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#define PSR_N ((PSR & PSR_N_BIT) != 0)
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#define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
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#define PSR_Z ((PSR & PSR_Z_BIT) != 0)
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#define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
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#define PSR_F ((PSR & PSR_F_BIT) != 0)
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#define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
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#define PSR_U ((PSR & PSR_U_BIT) != 0)
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#define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
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#define PSR_L ((PSR & PSR_L_BIT) != 0)
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#define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
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#define PSR_T ((PSR & PSR_T_BIT) != 0)
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#define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
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#define PSR_C ((PSR & PSR_C_BIT) != 0)
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#define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
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/* See simopsc.:move_to_cr() for registers that can not be read-from
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or assigned-to directly */
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#define PC CREG (PC_CR)
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#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
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//#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
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#define BPSR CREG (BPSR_CR)
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#define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
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#define BPC CREG (BPC_CR)
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#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
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#define DPSR CREG (DPSR_CR)
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#define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
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#define DPC CREG (DPC_CR)
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#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
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#define RPT_C CREG (RPT_C_CR)
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#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
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#define RPT_S CREG (RPT_S_CR)
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#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
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#define RPT_E CREG (RPT_E_CR)
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#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
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#define MOD_S CREG (MOD_S_CR)
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#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
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#define MOD_E CREG (MOD_E_CR)
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#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
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#define IBA CREG (IBA_CR)
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#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
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#define SIG_CR16_STOP -1
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#define SIG_CR16_EXIT -2
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#define SIG_CR16_BUS -3
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#define SIG_CR16_IAD -4
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/* TODO: Resolve conflicts with common headers. */
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#undef SEXT8
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#undef SEXT16
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#undef SEXT32
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#define SEXT3(x) ((((x)&0x7)^(~3))+4)
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/* sign-extend a 4-bit number */
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#define SEXT4(x) ((((x)&0xf)^(~7))+8)
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/* sign-extend an 8-bit number */
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#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
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/* sign-extend a 16-bit number */
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#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
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/* sign-extend a 24-bit number */
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#define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
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#define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
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#define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
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#define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
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#define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
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#define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
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/* Yes, this is as whacked as it looks. The sim currently reads little endian
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for 16 bits, but then merge them like big endian to get 32 bits. */
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static inline uint32_t get_longword (SIM_CPU *cpu, address_word addr)
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{
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return (RW (addr) << 16) | RW (addr + 2);
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}
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#define RLW(addr) get_longword (cpu, addr)
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#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
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#define RIE_VECTOR_START 0xffc2
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#define AE_VECTOR_START 0xffc3
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#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
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#define DBT_VECTOR_START 0xffd4
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#define SDBT_VECTOR_START 0xffd5
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#define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */
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#define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/
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#define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */
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#define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */
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#define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */
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#define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */
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/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
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cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
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(VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
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PSR is masked for zero bits. */
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extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p);
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#ifndef SIGTRAP
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#define SIGTRAP 5
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#endif
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/* Special purpose trap */
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#define TRAP_BREAKPOINT 8
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