mirror of
https://sourceware.org/git/binutils-gdb.git
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f57d151a99
* gdbarch.sh (NUM_REGS): Replace by gdbarch_num_regs. * i386-tdep.c (i386_dbx_reg_to_regnum) (i386_svr4_reg_to_regnum): Likewise. * inf-ptrace.c (inf_ptrace_fetch_registers) (inf_ptrace_store_registers): Likewise. * corelow.c (get_core_registers): Likewise. * i386-linux-nat.c (supply_gregset, fill_gregset) (i386_linux_fetch_inferior_registers) (i386_linux_store_inferior_registers): Likewise. * remote.c (init_remote_state,packet_reg_from_regnum) (packet_reg_from_pnum,process_g_packet,remote_fetch_registers) (remote_prepare_to_store,store_registers_using_G) (remote_store_registers,remote_arch_state): Likewise. * tracepoint.c (encode_actions): Likewise. * mi/mi-main.c (mi_cmd_data_list_register_names) (mi_cmd_data_list_changed_registers,mi_cmd_data_list_register_values) (mi_cmd_data_write_register_values): Likewise. * tui/tui-regs.c (tui_show_register_group) (tui_show_register_group): Likewise. * xtensa-tdep.h (FP_ALIAS): Likewise. * xtensa-tdep.c (xtensa_register_name,xtensa_register_type) (xtensa_reg_to_regnum,xtensa_pseudo_register_read) (xtensa_pseudo_register_write,xtensa_register_reggroup_p): Likewise. * win32-nat.c (do_win32_fetch_inferior_registers) (do_win32_store_inferior_registers,fetch_elf_core_registers * user-regs.h: Likewise (comment). * user-regs.c (user_reg, user_reg_map_name_to_regnum): Likewise. * trad-frame.c (trad_frame_alloc_saved_regs): Likewise. * target-descriptions.h: Likewise (comment). * target-descriptions.c (tdesc_use_registers): Likewise (comment). * target.c (debug_print_register): Likewise. * stack.c (frame_info): Likewise. * stabsread.c (define_symbol): Likewise. * sh64-tdep.c (sh64_do_pseudo_register,sh64_print_register) (sh64_media_print_registers_info) (sh64_compact_print_registers_info): Likewise. * rs6000-tdep.c (rs6000_register_sim_regno): Likewise. * rs6000-nat.c (fetch_register,store_register): Likewise. * remote-sim.c (one2one_register_sim_regno,gdbsim_fetch_register) (gdbsim_fetch_register,gdbsim_store_register): Likewise. * remote-mips.c (mips_fetch_registers,mips_store_registers): Likewise. * remote-m32r-sdi.c (m32r_fetch_registers) (m32r_store_registers): Likewise. * reggroups.c (default_register_reggroup_p): Likewise. * regcache.c (init_regcache_descr,register_size,regcache,regcache_save) (regcache_restore,regcache_dump): Likewise. * monitor.c (monitor_fetch_registers,monitor_store_registers): Likewise. * mips-tdep.c (mips_xfer_register,mips_register_name) (mips_register_reggroup_p,mips_pseudo_register_read) (mips_pseudo_register_write,mips_convert_register_p,mips_register_type) (mips_unwind_pc,mips_unwind_sp,mips_unwind_dummy_id,set_reg_offset) (mips16_scan_prologue,mips_insn16_frame_cache,reset_saved_regs) (mips32_scan_prologue,mips_insn32_frame_cache,read_next_frame_reg) (mips_n32n64_return_value,mips_o32_return_value,mips_o64_return_value) (print_gp_register_row,mips_print_registers_info) (mips_stab_reg_to_regnum,mips_dwarf_dwarf2_ecoff_reg_to_regnum) (mips_register_sim_regno): Likewise. * mips-linux-tdep.c (mips_linux_o32_sigframe_init) (mips_linux_n32n64_sigframe_init): Likewise. * mips-linux-nat.c (mips_linux_register_addr) (mips64_linux_register_addr): Likewise. * findvar.c (value_of_register): Likewise. * infcmd.c (default_print_registers_info,registers_info) (print_vector_info,print_float_info): Likewise. * mips64obsd-tdep.c (mips64obsd_sigframe_init): Likewise. * inf-child.c (inf_child_fetch_inferior_registers): Likewise. * m68k-tdep.c (m68k_dwarf_reg_to_regnum): Likewise. * m68hc11-tdep.c (m68hc11_frame_unwind_cache(: Likewise. * m32r-tdep.c (m32r_frame_unwind_cache): Likewise. * ia64-linux-nat.c (ia64_register_addr,ia64_cannot_fetch_register) (ia64_cannot_store_register,ia64_linux_fetch_registers) (ia64_linux_store_registers): Likewise. * hpux-thread.c (hpux_thread_fetch_registers) (hpux_thread_store_registers): Likewise. * h8300-tdep.c (E_PSEUDO_CCR_REGNUM,E_PSEUDO_EXR_REGNUM) (h8300_init_frame_cache,h8300_frame_cache,h8300_frame_prev_register) (h8300_register_type): Likewise. * dwarf2-frame.c (dwarf2_frame_cache) (dwarf2_frame_state_alloc_regs): Likewise. * cris-tdep.c (cris_register_size,cris_cannot_fetch_register) (cris_cannot_store_register,crisv32_cannot_fetch_register) (crisv32_cannot_store_register,cris_register_name): Likewise. * avr-tdep.c (avr_frame_unwind_cache): Likewise. * arch-utils.c (legacy_register_sim_regno) (legacy_virtual_frame_pointer): Likewise. * arm-tdep.c (arm_make_prologue_cache,arm_register_sim_regno):Likewise. * arm-tdep.h: Likewise (comment). * frv-tdep.c (frv_register_sim_regno): Likewise. * m68klinux-nat.c (old_fetch_inferior_registers) (old_store_inferior_registers): Likewise. * m32c-tdep.c (m32c_virtual_frame_pointer): Likewise. * irix5-nat.c (fetch_core_registers): Likewise. * hppa-tdep.c (hppa_frame_cache): Likewise. * hppa-linux-nat.c (hppa_linux_register_addr) (hppa_linux_fetch_inferior_registers) (hppa_linux_store_inferior_registers): Likewise. * hppa-hpux-nat.c (hppa_hpux_fetch_inferior_registers) (hppa_hpux_store_inferior_registers): Likewise. * amd64-nat.c (amd64_native_gregset_reg_offset) (amd64_supply_native_gregset,amd64_collect_native_gregset): Likewise. * dbug-rom.c (dbug_regname): Likewise. * m68hc11-tdep.c (m68hc11_frame_unwind_cache) (HARD_PAGE_REGNUM (comment)): Likewise. * gdbarch.sh (NUM_PSEUDO_REGS): Replace by gdbarch_num_pseudo_regs. * i386-tdep.c (i386_dbx_reg_to_regnum) (i386_svr4_reg_to_regnum): Likewise. * mi/mi-main.c (mi_cmd_data_list_register_names) (mi_cmd_data_list_changed_registers,mi_cmd_data_list_register_values) (mi_cmd_data_write_register_values): Likewise. * gdbarch.c, gdbarch.h: Regenerate. * tui/tui-regs.c (tui_show_register_group): Likewise. * xtensa-tdep.h (FP_ALIAS): Likewise. * user-regs.h: Likewise (comment). * user-regs.c (user_reg, user_reg_map_name_to_regnum): Likewise. * trad-frame.c (trad_frame_alloc_saved_regs): Likewise. * target-descriptions.h: Likewise (comment). * target.c (debug_print_register): Likewise. * stack.c (frame_info): Likewise. * stabsread.c (define_symbol): Likewise. * sh64-tdep.c (sh64_print_register,sh64_media_print_registers_info) (sh64_compact_print_registers_info): Likewise. * rs6000-tdep.c (rs6000_register_sim_regno): Likewise. * regcache.c (init_regcache_descr,register_size,regcache,regcache_save (regcache_restore,regcache_dump): Likewise. * mips-tdep.c (print_gp_register_row,mips_print_registers_info) (mips_dwarf_dwarf2_ecoff_reg_to_regnum) (mips_stab_reg_to_regnum): Likewise. * findvar.c (value_of_register): Likewise. * infcmd.c (default_print_registers_info,registers_info) (print_vector_info,print_float_info): Likewise. * m68k-tdep.c (m68k_dwarf_reg_to_regnum): Likewise. * h8300-tdep.c (h8300_register_type): Likewise. * dwarf2-frame.c (dwarf2_frame_cache): Likewise. * frame.h (SIZEOF_FRAME_SAVED_REGS): Likewise. * xtensa-tdep.c (xtensa_register_type,xtensa_reg_to_regnum) (xtensa_pseudo_register_read,xtensa_pseudo_register_write): Likewise. * parse.c: Remove comment. * gdbarch.c, gdbarch.h: Regenerate
197 lines
6.4 KiB
C
197 lines
6.4 KiB
C
/* Common target dependent code for GDB on ARM systems.
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Copyright (C) 2002, 2003, 2007 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#ifndef ARM_TDEP_H
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#define ARM_TDEP_H
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/* Forward declarations. */
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struct gdbarch;
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struct regset;
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/* Register numbers of various important registers. */
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enum gdb_regnum {
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ARM_A1_REGNUM = 0, /* first integer-like argument */
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ARM_A4_REGNUM = 3, /* last integer-like argument */
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ARM_AP_REGNUM = 11,
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ARM_SP_REGNUM = 13, /* Contains address of top of stack */
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ARM_LR_REGNUM = 14, /* address to return to from a function call */
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ARM_PC_REGNUM = 15, /* Contains program counter */
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ARM_F0_REGNUM = 16, /* first floating point register */
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ARM_F3_REGNUM = 19, /* last floating point argument register */
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ARM_F7_REGNUM = 23, /* last floating point register */
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ARM_FPS_REGNUM = 24, /* floating point status register */
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ARM_PS_REGNUM = 25, /* Contains processor status */
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ARM_WR0_REGNUM, /* WMMX data registers. */
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ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
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ARM_WC0_REGNUM, /* WMMX control registers. */
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ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
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ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
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ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
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ARM_WCGR0_REGNUM, /* WMMX general purpose registers. */
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ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
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ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
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ARM_NUM_REGS,
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/* Other useful registers. */
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ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */
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THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */
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ARM_NUM_ARG_REGS = 4,
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ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM,
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ARM_NUM_FP_ARG_REGS = 4,
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ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM
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};
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/* Size of integer registers. */
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#define INT_REGISTER_SIZE 4
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/* Say how long FP registers are. Used for documentation purposes and
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code readability in this header. IEEE extended doubles are 80
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bits. DWORD aligned they use 96 bits. */
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#define FP_REGISTER_SIZE 12
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/* Status registers are the same size as general purpose registers.
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Used for documentation purposes and code readability in this
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header. */
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#define STATUS_REGISTER_SIZE 4
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/* Number of machine registers. The only define actually required
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is gdbarch_num_regs. The other definitions are used for documentation
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purposes and code readability. */
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/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
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(and called PS for processor status) so the status bits can be cleared
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from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
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in PS. */
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#define NUM_FREGS 8 /* Number of floating point registers. */
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#define NUM_SREGS 2 /* Number of status registers. */
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#define NUM_GREGS 16 /* Number of general purpose registers. */
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/* Instruction condition field values. */
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#define INST_EQ 0x0
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#define INST_NE 0x1
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#define INST_CS 0x2
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#define INST_CC 0x3
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#define INST_MI 0x4
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#define INST_PL 0x5
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#define INST_VS 0x6
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#define INST_VC 0x7
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#define INST_HI 0x8
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#define INST_LS 0x9
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#define INST_GE 0xa
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#define INST_LT 0xb
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#define INST_GT 0xc
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#define INST_LE 0xd
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#define INST_AL 0xe
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#define INST_NV 0xf
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#define FLAG_N 0x80000000
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#define FLAG_Z 0x40000000
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#define FLAG_C 0x20000000
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#define FLAG_V 0x10000000
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/* Type of floating-point code in use by inferior. There are really 3 models
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that are traditionally supported (plus the endianness issue), but gcc can
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only generate 2 of those. The third is APCS_FLOAT, where arguments to
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functions are passed in floating-point registers.
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In addition to the traditional models, VFP adds two more.
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If you update this enum, don't forget to update fp_model_strings in
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arm-tdep.c. */
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enum arm_float_model
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{
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ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
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ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
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ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
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ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
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ARM_FLOAT_VFP, /* Full VFP calling convention. */
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ARM_FLOAT_LAST /* Keep at end. */
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};
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/* ABI used by the inferior. */
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enum arm_abi_kind
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{
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ARM_ABI_AUTO,
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ARM_ABI_APCS,
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ARM_ABI_AAPCS,
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ARM_ABI_LAST
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};
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/* Convention for returning structures. */
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enum struct_return
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{
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pcc_struct_return, /* Return "short" structures in memory. */
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reg_struct_return /* Return "short" structures in registers. */
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};
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/* Target-dependent structure in gdbarch. */
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struct gdbarch_tdep
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{
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/* The ABI for this architecture. It should never be set to
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ARM_ABI_AUTO. */
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enum arm_abi_kind arm_abi;
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enum arm_float_model fp_model; /* Floating point calling conventions. */
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int have_fpa_registers; /* Does the target report the FPA registers? */
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CORE_ADDR lowest_pc; /* Lowest address at which instructions
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will appear. */
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const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */
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int arm_breakpoint_size; /* And its size. */
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const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */
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int thumb_breakpoint_size; /* And its size. */
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int jb_pc; /* Offset to PC value in jump buffer.
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If this is negative, longjmp support
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will be disabled. */
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size_t jb_elt_size; /* And the size of each entry in the buf. */
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/* Convention for returning structures. */
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enum struct_return struct_return;
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/* Cached core file helpers. */
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struct regset *gregset, *fpregset;
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};
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#ifndef LOWEST_PC
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#define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
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#endif
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int arm_software_single_step (struct regcache *);
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/* Functions exported from armbsd-tdep.h. */
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/* Return the appropriate register set for the core section identified
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by SECT_NAME and SECT_SIZE. */
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extern const struct regset *
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armbsd_regset_from_core_section (struct gdbarch *gdbarch,
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const char *sect_name, size_t sect_size);
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#endif /* arm-tdep.h */
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