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https://sourceware.org/git/binutils-gdb.git
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6a2619f953
With this change all gas and most ld tests pass when configured for arm-linux. It doesn't look like these configurations have been tested in a long time but this attempts to stem the bit-rot slightly. gas/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * gas/arm/bl-local-2.d: Only enable the test on EABI and NaCl configurations. * gas/arm/bl-local-v4t.d: Likewise. * gas/arm/blx-local.d: Likewise. * gas/arm/branch-reloc.d: Likewise. ld/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * ld-arm/arm-elf.exp (armelftests_nonacl): Move Cortex-A8 fix tests, IFUNC tests and other EABI requiring tests to... (armeabitests_nonacl): ...here. * ld-arm/arm-app-abs32.d: Loosen regex for architecture type to allow test to pass on configurations without an attributes section. * ld-arm/arm-app.d: Likewise. * ld-arm/arm-lib-plt32.d: Likewise. * ld-arm/arm-lib.d: Likewise. * ld-arm/arm-static-app.d: Likewise. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/cortex-a8-far.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. * ld-arm/tls-app.d: Likewise. * ld-arm/tls-descrelax-be32.d: Likewise. * ld-arm/tls-descrelax.d: Likewise. * ld-arm/tls-descseq.d: Likewise. * ld-arm/tls-gdesc-got.d: Likewise. * ld-arm/tls-gdesc.d: Likewise. * ld-arm/tls-gdierelax.d: Likewise. * ld-arm/tls-gdierelax2.d: Likewise. * ld-arm/tls-gdlerelax.d: Likewise. * ld-arm/tls-lib-loc.d: Likewise. * ld-arm/tls-lib.d: Likewise. * ld-arm/tls-thumb1.d: Likewise.
45 lines
1.4 KiB
Makefile
45 lines
1.4 KiB
Makefile
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tmpdir/tls-lib2inline.so: file format elf32-.*arm
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architecture: arm.*, flags 0x[0-9a-f]+:
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HAS_SYMS, DYNAMIC, D_PAGED
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start address 0x[0-9a-f]+
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Disassembly of section .plt:
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[0-9a-f]+ <.plt>:
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[0-9a-f]+: e52de004 push {lr} ; .*
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[0-9a-f]+: e59fe004 ldr lr, \[pc, #4\] ; .*
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[0-9a-f]+: e08fe00e add lr, pc, lr
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[0-9a-f]+: e5bef008 ldr pc, \[lr, #8\]!
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[0-9a-f]+: 000080e4 .word 0x000080e4
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[0-9a-f]+: e08e0000 add r0, lr, r0
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[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
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[0-9a-f]+: e12fff11 bx r1
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[0-9a-f]+: e52d2004 push {r2} ; .*
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[0-9a-f]+: e59f200c ldr r2, \[pc, #12\] ; .*
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[0-9a-f]+: e59f100c ldr r1, \[pc, #12\] ; .*
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[0-9a-f]+: e79f2002 ldr r2, \[pc, r2\]
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[0-9a-f]+: e081100f add r1, r1, pc
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[0-9a-f]+: e12fff12 bx r2
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[0-9a-f]+: 000080d4 .word 0x000080d4
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[0-9a-f]+: 000080bc .word 0x000080bc
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Disassembly of section .text:
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[0-9a-f]+ <foo>:
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[0-9a-f]+: e59f000c ldr r0, \[pc, #12\] ; .*
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[0-9a-f]+: e08f0000 add r0, pc, r0
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[0-9a-f]+: e5901004 ldr r1, \[r0, #4\]
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[0-9a-f]+: e12fff31 blx r1
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[0-9a-f]+: e1a00000 nop ; .*
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[0-9a-f]+: 000080b4 .word 0x000080b4
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[0-9a-f]+ <bar>:
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[0-9a-f]+: 4802 ldr r0, \[pc, #8\] ; .*
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[0-9a-f]+: 4478 add r0, pc
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[0-9a-f]+: 6841 ldr r1, \[r0, #4\]
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[0-9a-f]+: 4788 blx r1
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[0-9a-f]+: 46c0 nop ; .*
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[0-9a-f]+: 46c0 nop ; .*
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[0-9a-f]+: 000080a2 .word 0x000080a2
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