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6177c84d5e
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
51 lines
978 B
C
51 lines
978 B
C
/* X86_64_EVEX_0F90 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F90_L_0) },
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},
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/* X86_64_EVEX_0F91 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F91_L_0) },
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},
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/* X86_64_EVEX_0F92 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F92_L_0) },
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},
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/* X86_64_EVEX_0F93 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F93_L_0) },
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},
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/* X86_64_EVEX_0F38F2 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
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},
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/* X86_64_EVEX_0F38F3 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
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},
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/* X86_64_EVEX_0F38F5 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_0F38F5_L_0) },
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},
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/* X86_64_EVEX_0F38F6 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
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},
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/* X86_64_EVEX_0F38F7 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
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},
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/* X86_64_EVEX_0F3AF0 */
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{
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
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},
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