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767a879e31
This commit does two things: 1. Makes use of the DECLARE_CSR_ALIAS definitions in riscv-opc.h to add additional aliases for CSRs. 2. Only creates aliases for registers that are actually present on the target (as announced in the target XML description). This means that the 'csr%d' aliases that exist will only be created for those CSRs the target actually has, which is a nice improvement, as accessing one of the CSRs that didn't exist would cause GDB to crash with this error: valprint.c:1560: internal-error: bool maybe_negate_by_bytes(const gdb_byte*, unsigned int, bfd_endian, gdb::byte_vector*): Assertion `len > 0' failed. When we look at the DECLARE_CSR_ALIAS lines in riscv-opc.h, these can be split into three groups: DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1) The 'misa' register used to exist of offset 0xf10, but was moved to its current offset (0x301) in with privilege spec 1.9.1. We don't want GDB to create an alias called 'misa' as we will already have a 'misa' register created by the DECLARE_CSR(misa ....) call earlier in riscv-opc.h DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10) These aliases are all CSRs that were removed in privilege spec 1.10, and whose addresses were reused by new CSRs. The names meaning of the old names is totally different to the new CSRs that have taken their place. I don't believe we should add these as aliases into GDB. If the new CSR exists in the target then that should be enough. DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11) In privilege spec 1.11 the 'dscratch' register was renamed to 'dscratch0', however the meaning of the register didn't change. Adding the 'dscratch' alias makes sense I think. Looking then at the final PRIV_SPEC_CLASS_* field for each alias then we can see that currently we only want to take the alias from PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter the aliases within GDB. In the future there's no telling how DECLARE_CSR_ALIAS will be used. I've heard it said that future RISC-V privilege specs will not reuse CSR offsets again. But it could happen. We just don't know. If / when it does we may need to revisit how aliases are created for GDB, but for now this seems to be OK. gdb/ChangeLog: * riscv-tdep.c (riscv_create_csr_aliases): Handle csr aliases from riscv-opc.h. (class riscv_pending_register_alias): New class. (riscv_check_tdesc_feature): Take vector of pending aliases and populate it as appropriate. (riscv_setup_register_aliases): Delete. (riscv_gdbarch_init): Create vector of pending aliases and pass it to riscv_check_tdesc_feature in all cases. Use the vector to create the register aliases. gdb/testsuite/ChangeLog: * gdb.arch/riscv-tdesc-regs-32.xml: New file. * gdb.arch/riscv-tdesc-regs-64.xml: New file. * gdb.arch/riscv-tdesc-regs.c: New file. * gdb.arch/riscv-tdesc-regs.exp: New file.
94 lines
4.3 KiB
XML
94 lines
4.3 KiB
XML
<?xml version="1.0"?>
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>riscv</architecture>
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<feature name="org.gnu.gdb.riscv.cpu">
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<reg name="zero" bitsize="64" type="int"/>
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<reg name="ra" bitsize="64" type="code_ptr"/>
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<reg name="sp" bitsize="64" type="data_ptr"/>
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<reg name="gp" bitsize="64" type="data_ptr"/>
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<reg name="tp" bitsize="64" type="data_ptr"/>
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<reg name="t0" bitsize="64" type="int"/>
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<reg name="t1" bitsize="64" type="int"/>
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<reg name="t2" bitsize="64" type="int"/>
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<reg name="fp" bitsize="64" type="data_ptr"/>
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<reg name="s1" bitsize="64" type="int"/>
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<reg name="a0" bitsize="64" type="int"/>
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<reg name="a1" bitsize="64" type="int"/>
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<reg name="a2" bitsize="64" type="int"/>
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<reg name="a3" bitsize="64" type="int"/>
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<reg name="a4" bitsize="64" type="int"/>
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<reg name="a5" bitsize="64" type="int"/>
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<reg name="a6" bitsize="64" type="int"/>
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<reg name="a7" bitsize="64" type="int"/>
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<reg name="s2" bitsize="64" type="int"/>
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<reg name="s3" bitsize="64" type="int"/>
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<reg name="s4" bitsize="64" type="int"/>
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<reg name="s5" bitsize="64" type="int"/>
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<reg name="s6" bitsize="64" type="int"/>
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<reg name="s7" bitsize="64" type="int"/>
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<reg name="s8" bitsize="64" type="int"/>
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<reg name="s9" bitsize="64" type="int"/>
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<reg name="s10" bitsize="64" type="int"/>
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<reg name="s11" bitsize="64" type="int"/>
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<reg name="t3" bitsize="64" type="int"/>
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<reg name="t4" bitsize="64" type="int"/>
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<reg name="t5" bitsize="64" type="int"/>
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<reg name="t6" bitsize="64" type="int"/>
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<reg name="pc" bitsize="64" type="code_ptr"/>
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</feature>
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<feature name="org.gnu.gdb.riscv.fpu">
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<union id="riscv_double">
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<field name="float" type="ieee_single"/>
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<field name="double" type="ieee_double"/>
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</union>
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<reg name="ft0" bitsize="64" type="riscv_double"/>
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<reg name="ft1" bitsize="64" type="riscv_double"/>
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<reg name="ft2" bitsize="64" type="riscv_double"/>
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<reg name="ft3" bitsize="64" type="riscv_double"/>
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<reg name="ft4" bitsize="64" type="riscv_double"/>
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<reg name="ft5" bitsize="64" type="riscv_double"/>
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<reg name="ft6" bitsize="64" type="riscv_double"/>
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<reg name="ft7" bitsize="64" type="riscv_double"/>
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<reg name="fs0" bitsize="64" type="riscv_double"/>
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<reg name="fs1" bitsize="64" type="riscv_double"/>
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<reg name="fa0" bitsize="64" type="riscv_double"/>
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<reg name="fa1" bitsize="64" type="riscv_double"/>
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<reg name="fa2" bitsize="64" type="riscv_double"/>
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<reg name="fa3" bitsize="64" type="riscv_double"/>
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<reg name="fa4" bitsize="64" type="riscv_double"/>
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<reg name="fa5" bitsize="64" type="riscv_double"/>
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<reg name="fa6" bitsize="64" type="riscv_double"/>
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<reg name="fa7" bitsize="64" type="riscv_double"/>
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<reg name="fs2" bitsize="64" type="riscv_double"/>
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<reg name="fs3" bitsize="64" type="riscv_double"/>
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<reg name="fs4" bitsize="64" type="riscv_double"/>
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<reg name="fs5" bitsize="64" type="riscv_double"/>
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<reg name="fs6" bitsize="64" type="riscv_double"/>
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<reg name="fs7" bitsize="64" type="riscv_double"/>
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<reg name="fs8" bitsize="64" type="riscv_double"/>
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<reg name="fs9" bitsize="64" type="riscv_double"/>
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<reg name="fs10" bitsize="64" type="riscv_double"/>
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<reg name="fs11" bitsize="64" type="riscv_double"/>
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<reg name="ft8" bitsize="64" type="riscv_double"/>
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<reg name="ft9" bitsize="64" type="riscv_double"/>
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<reg name="ft10" bitsize="64" type="riscv_double"/>
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<reg name="ft11" bitsize="64" type="riscv_double"/>
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<!-- The following 3 registers are duplicated. -->
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<reg name="fflags" bitsize="32" type="int"/>
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<reg name="frm" bitsize="32" type="int"/>
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<reg name="fcsr" bitsize="32" type="int"/>
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</feature>
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<feature name="org.gnu.gdb.riscv.csr">
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<!-- The following 3 registers are duplicated. -->
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<reg name="fflags" bitsize="32" type="int"/>
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<reg name="frm" bitsize="32" type="int"/>
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<reg name="fcsr" bitsize="32" type="int"/>
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<!-- The following is a CSR unknown to GDB. -->
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<reg name="unknown_csr" bitsize="32" type="int"/>
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<!-- The following is now known as 'dscratch0' in the official
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RISC-V spec, but GDB should NOT rename this register. -->
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<reg name="dscratch" bitsize="32" type="int"/>
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</feature>
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</target>
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