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345bd07cce
I would like to be able to use non-trivial types in gdbarch_tdep types. This is not possible at the moment (in theory), because of the one definition rule. To allow it, rename all gdbarch_tdep types to <arch>_gdbarch_tdep, and make them inherit from a gdbarch_tdep base class. The inheritance is necessary to be able to pass pointers to all these <arch>_gdbarch_tdep objects to gdbarch_alloc, which takes a pointer to gdbarch_tdep. These objects are never deleted through a base class pointer, so I didn't include a virtual destructor. In the future, if gdbarch objects deletable, I could imagine that the gdbarch_tdep objects could become owned by the gdbarch objects, and then it would become useful to have a virtual destructor (so that the gdbarch object can delete the owned gdbarch_tdep object). But that's not necessary right now. It turns out that RISC-V already has a gdbarch_tdep that is non-default-constructible, so that provides a good motivation for this change. Most changes are fairly straightforward, mostly needing to add some casts all over the place. There is however the xtensa architecture, doing its own little weird thing to define its gdbarch_tdep. I did my best to adapt it, but I can't test those changes. Change-Id: Ic001903f91ddd106bd6ca09a79dabe8df2d69f3b
214 lines
6.4 KiB
C
214 lines
6.4 KiB
C
/* none on ARM target support.
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Copyright (C) 2020-2021 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "arm-tdep.h"
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#include "arch-utils.h"
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#include "regcache.h"
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#include "elf-bfd.h"
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#include "regset.h"
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#include "user-regs.h"
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#ifdef HAVE_ELF
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#include "elf-none-tdep.h"
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#endif
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/* Core file and register set support. */
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#define ARM_NONE_SIZEOF_GREGSET (18 * ARM_INT_REGISTER_SIZE)
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/* Support VFP register format. */
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#define ARM_NONE_SIZEOF_VFP (32 * 8 + 4)
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/* The index to access CPSR in user_regs as defined in GLIBC. */
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#define ARM_NONE_CPSR_GREGNUM 16
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/* Supply register REGNUM from buffer GREGS_BUF (length LEN bytes) into
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REGCACHE. If REGNUM is -1 then supply all registers. The set of
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registers that this function will supply is limited to the general
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purpose registers.
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The layout of the registers here is based on the ARM GNU/Linux
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layout. */
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static void
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arm_none_supply_gregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *gregs_buf, size_t len)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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const gdb_byte *gregs = (const gdb_byte *) gregs_buf;
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for (int regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
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if (regnum == -1 || regnum == regno)
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regcache->raw_supply (regno, gregs + ARM_INT_REGISTER_SIZE * regno);
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if (regnum == ARM_PS_REGNUM || regnum == -1)
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{
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if (arm_apcs_32)
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regcache->raw_supply (ARM_PS_REGNUM,
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gregs + ARM_INT_REGISTER_SIZE
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* ARM_NONE_CPSR_GREGNUM);
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else
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regcache->raw_supply (ARM_PS_REGNUM,
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gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
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}
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if (regnum == ARM_PC_REGNUM || regnum == -1)
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{
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gdb_byte pc_buf[ARM_INT_REGISTER_SIZE];
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CORE_ADDR reg_pc
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= extract_unsigned_integer (gregs + ARM_INT_REGISTER_SIZE
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* ARM_PC_REGNUM,
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ARM_INT_REGISTER_SIZE, byte_order);
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reg_pc = gdbarch_addr_bits_remove (gdbarch, reg_pc);
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store_unsigned_integer (pc_buf, ARM_INT_REGISTER_SIZE, byte_order,
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reg_pc);
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regcache->raw_supply (ARM_PC_REGNUM, pc_buf);
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}
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}
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/* Collect register REGNUM from REGCACHE and place it into buffer GREGS_BUF
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(length LEN bytes). If REGNUM is -1 then collect all registers. The
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set of registers that this function will collect is limited to the
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general purpose registers.
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The layout of the registers here is based on the ARM GNU/Linux
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layout. */
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static void
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arm_none_collect_gregset (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *gregs_buf, size_t len)
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{
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gdb_byte *gregs = (gdb_byte *) gregs_buf;
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for (int regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++)
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if (regnum == -1 || regnum == regno)
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regcache->raw_collect (regno,
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gregs + ARM_INT_REGISTER_SIZE * regno);
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if (regnum == ARM_PS_REGNUM || regnum == -1)
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{
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if (arm_apcs_32)
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regcache->raw_collect (ARM_PS_REGNUM,
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gregs + ARM_INT_REGISTER_SIZE
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* ARM_NONE_CPSR_GREGNUM);
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else
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regcache->raw_collect (ARM_PS_REGNUM,
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gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
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}
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if (regnum == ARM_PC_REGNUM || regnum == -1)
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regcache->raw_collect (ARM_PC_REGNUM,
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gregs + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM);
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}
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/* Supply VFP registers from REGS_BUF into REGCACHE. */
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static void
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arm_none_supply_vfp (const struct regset *regset,
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struct regcache *regcache,
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int regnum, const void *regs_buf, size_t len)
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{
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const gdb_byte *regs = (const gdb_byte *) regs_buf;
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if (regnum == ARM_FPSCR_REGNUM || regnum == -1)
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regcache->raw_supply (ARM_FPSCR_REGNUM, regs + 32 * 8);
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for (int regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++)
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if (regnum == -1 || regnum == regno)
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regcache->raw_supply (regno, regs + (regno - ARM_D0_REGNUM) * 8);
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}
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/* Collect VFP registers from REGCACHE into REGS_BUF. */
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static void
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arm_none_collect_vfp (const struct regset *regset,
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const struct regcache *regcache,
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int regnum, void *regs_buf, size_t len)
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{
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gdb_byte *regs = (gdb_byte *) regs_buf;
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if (regnum == ARM_FPSCR_REGNUM || regnum == -1)
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regcache->raw_collect (ARM_FPSCR_REGNUM, regs + 32 * 8);
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for (int regno = ARM_D0_REGNUM; regno <= ARM_D31_REGNUM; regno++)
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if (regnum == -1 || regnum == regno)
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regcache->raw_collect (regno, regs + (regno - ARM_D0_REGNUM) * 8);
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}
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/* The general purpose register set. */
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static const struct regset arm_none_gregset =
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{
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nullptr, arm_none_supply_gregset, arm_none_collect_gregset
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};
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/* The VFP register set. */
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static const struct regset arm_none_vfpregset =
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{
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nullptr, arm_none_supply_vfp, arm_none_collect_vfp
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};
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/* Iterate over core file register note sections. */
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static void
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arm_none_iterate_over_regset_sections (struct gdbarch *gdbarch,
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iterate_over_regset_sections_cb *cb,
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void *cb_data,
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const struct regcache *regcache)
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{
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arm_gdbarch_tdep *tdep = (arm_gdbarch_tdep *) gdbarch_tdep (gdbarch);
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cb (".reg", ARM_NONE_SIZEOF_GREGSET, ARM_NONE_SIZEOF_GREGSET,
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&arm_none_gregset, nullptr, cb_data);
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if (tdep->vfp_register_count > 0)
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cb (".reg-arm-vfp", ARM_NONE_SIZEOF_VFP, ARM_NONE_SIZEOF_VFP,
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&arm_none_vfpregset, "VFP floating-point", cb_data);
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}
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/* Initialize ARM bare-metal ABI info. */
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static void
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arm_none_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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#ifdef HAVE_ELF
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elf_none_init_abi (gdbarch);
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#endif
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/* Iterate over registers for reading and writing bare metal ARM core
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files. */
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set_gdbarch_iterate_over_regset_sections
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(gdbarch, arm_none_iterate_over_regset_sections);
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}
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/* Initialize ARM bare-metal target support. */
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void _initialize_arm_none_tdep ();
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void
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_initialize_arm_none_tdep ()
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{
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gdbarch_register_osabi (bfd_arch_arm, 0, GDB_OSABI_NONE,
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arm_none_init_abi);
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}
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