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144bed8d4d
Relocations against .got.plt section may not be in the same order as entries in PLT section. It is incorrect to assume that the Ith reloction index against .got.plt section always maps to the (I + 1)th entry in PLT section. This patch matches the .got.plt relocation offset/index in PLT entry against the index in .got.plt relocation table. It only checks R_*_JUMP_SLOT and R_*_IRELATIVE relocations. It ignores R_*_TLS_DESC and R_*_TLSDESC relocations since they have different PLT entries. bfd/ PR binutils/17154 * elf32-i386.c (elf_i386_plt_sym_val): Only match R_*_JUMP_SLOT and R_*_IRELATIVE relocation offset with PLT entry. * elf64-x86-64.c (elf_x86_64_plt_sym_val): Likewise. (elf_x86_64_plt_sym_val_offset_plt_bnd): New. (elf_x86_64_get_synthetic_symtab): Use it. ld/testsuite/ PR binutils/17154 * ld-ifunc/pr17154-i386.d: New file. * ld-ifunc/pr17154-x86-64.d: Likewise. * ld-ifunc/pr17154-x86.s: Likewise. * ld-x86-64/bnd-ifunc-2.d: Likewise. * ld-x86-64/bnd-ifunc-2.s: Likewise. * ld-x86-64/mpx.exp: Run bnd-ifunc-2. * ld-x86-64/tlsdesc-nacl.pd: Updated. * ld-x86-64/tlsdesc.pd: Likewise.
41 lines
1.8 KiB
Plaintext
41 lines
1.8 KiB
Plaintext
#source: tlsdesc.s
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#source: tlspic2.s
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#as: --64
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#ld: -shared -melf_x86_64_nacl --no-ld-generated-unwind-info
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#objdump: -drj.plt
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#target: x86_64-*-nacl*
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.*: +file format elf64-x86-64-nacl
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Disassembly of section .plt:
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[0-9a-f]+ <.plt>:
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+[0-9a-f]+: ff 35 .. .. .. .. pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
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+[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
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+[0-9a-f]+: 4d 01 fb add %r15,%r11
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+[0-9a-f]+: 41 ff e3 jmpq \*%r11
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+[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 00 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 90 xchg %ax,%ax
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+[0-9a-f]+: ff 35 .. .. .. .. pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
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+[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x190>
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+[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
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+[0-9a-f]+: 4d 01 fb add %r15,%r11
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+[0-9a-f]+: 41 ff e3 jmpq \*%r11
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+[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 00 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
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+[0-9a-f]+: 0f 1f 84 00 00 00 00 *
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+[0-9a-f]+: 00 *
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+[0-9a-f]+: 66 90 xchg %ax,%ax
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