binutils-gdb/gdb/arch/riscv.h
Andrew Burgess 96f842cbdb gdb/riscv: add support for vector registers in target descriptions
This commit adds support to RISC-V GDB for vector registers in the
incoming target description.

The vector registers should be described in a feature called
"org.gnu.gdb.riscv.vector", and should contain the register v0 to
v31.  There's no restriction on the size or type of these registers,
so the target description can set these up as it requires.

However, if the target feature is present then all of the registers
must be present, and they must all be the same size, these
requirements are, I believe, inline with the RISC-V vector extension.

The DWARF register numbers for the vector registers have been added,
and the code to map between GDB's internal numbering and the DWARF
numbering has been updated.

I have not yet added a feature/riscv/*.xml file for the vector
extension, the consequence of this is that we can't, right now, detect
vector registers on a native target, this patch is all about
supporting vectors on a remote target.

It is worth noting that I don't actually have access to a RISC-V
target with vectors, so the only testing that this patch has had has
been done using 'set tdesc filename ....' to load a target description
to which I have manually added the vector feature.  This has shown
that the vector register feature can be successfully parsed, and that
the registers show up in the expected register groups.

Additionally, the RISC-V vector extension is currently at v0.10, which
is also the v1.0 draft release.  However, this extension is not yet
finalised.  It is possible (but unlikely I think) that the register
set could change between now and the final release of the vector
extension.  If this were to happen then we would potentially end up
changing the requirements for the new org.gnu.gdb.riscv.vector
feature.  I really don't think it is likely that the register set will
change this late in the process, and even if it did, changing the
feature requirements will not be a problem as far as I am
concerned (when the alternative is GDB just continues without this
feature for now).

gdb/ChangeLog:

	* NEWS: Mention new target feature name.
	* arch/riscv.c (riscv_create_target_description): GDB doesn't
	currently create target descriptions containing vector registers.
	* arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member
	variable.
	<operator==>: Also compare vlen.
	<hash>: Also include vlen.
	* riscv-tdep.c (riscv_feature_name_vector): New static global.
	(struct riscv_vector_feature): New struct.
	(riscv_vector_feature): New static global.
	(riscv_register_reggroup_p): Ensure vector registers are part of
	the 'all' group, and part of the 'vector' group.
	(riscv_dwarf_reg_to_regnum): Handle vector registers.
	(riscv_gdbarch_init): Check vector register feature.
	* riscv-tdep.h: Add vector registers to GDB's internal register
	numbers, and to the DWARF register numbers.

gdb/doc/ChangeLog:

	* gdb.texinfo (RISC-V Features): Mention vector register feature.
2021-06-21 20:47:13 +01:00

107 lines
3.7 KiB
C++

/* Common target-dependent functionality for RISC-V
Copyright (C) 2018-2021 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef ARCH_RISCV_H
#define ARCH_RISCV_H
#include "gdbsupport/tdesc.h"
/* The set of RISC-V architectural features that we track that impact how
we configure the actual gdbarch instance. We hold one of these in the
gdbarch_tdep structure, and use it to distinguish between different
RISC-V gdbarch instances.
The information in here ideally comes from the target description,
however, if the target doesn't provide a target description then we will
create a default target description by first populating one of these
based on what we know about the binary being executed, and using that to
drive default target description creation. */
struct riscv_gdbarch_features
{
/* The size of the x-registers in bytes. This is either 4 (RV32), 8
(RV64), or 16 (RV128). No other value is valid. Initialise to the
invalid 0 value so we can spot if one of these is used
uninitialised. */
int xlen = 0;
/* The size of the f-registers in bytes. This is either 4 (RV32), 8
(RV64), or 16 (RV128). This can also hold the value 0 to indicate
that there are no f-registers. No other value is valid. */
int flen = 0;
/* The size of the v-registers in bytes. The value 0 indicates a target
with no vector registers. The minimum value for a standard compliant
target should be 16, but GDB doesn't currently mind, and will accept
any vector size. */
int vlen = 0;
/* When true this target is RV32E. */
bool embedded = false;
/* Equality operator. */
bool operator== (const struct riscv_gdbarch_features &rhs) const
{
return (xlen == rhs.xlen && flen == rhs.flen
&& embedded == rhs.embedded && vlen == rhs.vlen);
}
/* Inequality operator. */
bool operator!= (const struct riscv_gdbarch_features &rhs) const
{
return !((*this) == rhs);
}
/* Used by std::unordered_map to hash feature sets. */
std::size_t hash () const noexcept
{
std::size_t val = ((embedded ? 1 : 0) << 10
| (xlen & 0x1f) << 5
| (flen & 0x1f) << 0
| (vlen & 0xfff) << 11);
return val;
}
};
#ifdef GDBSERVER
/* Create and return a target description that is compatible with FEATURES.
This is only used directly from the gdbserver where the created target
description is modified after it is return. */
target_desc_up riscv_create_target_description
(const struct riscv_gdbarch_features features);
#else
/* Lookup an already existing target description matching FEATURES, or
create a new target description if this is the first time we have seen
FEATURES. For the same FEATURES the same target_desc is always
returned. This is important when trying to lookup gdbarch objects as
GDBARCH_LIST_LOOKUP_BY_INFO performs a pointer comparison on target
descriptions to find candidate gdbarch objects. */
const target_desc *riscv_lookup_target_description
(const struct riscv_gdbarch_features features);
#endif /* GDBSERVER */
#endif /* ARCH_RISCV_H */