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96f842cbdb
This commit adds support to RISC-V GDB for vector registers in the incoming target description. The vector registers should be described in a feature called "org.gnu.gdb.riscv.vector", and should contain the register v0 to v31. There's no restriction on the size or type of these registers, so the target description can set these up as it requires. However, if the target feature is present then all of the registers must be present, and they must all be the same size, these requirements are, I believe, inline with the RISC-V vector extension. The DWARF register numbers for the vector registers have been added, and the code to map between GDB's internal numbering and the DWARF numbering has been updated. I have not yet added a feature/riscv/*.xml file for the vector extension, the consequence of this is that we can't, right now, detect vector registers on a native target, this patch is all about supporting vectors on a remote target. It is worth noting that I don't actually have access to a RISC-V target with vectors, so the only testing that this patch has had has been done using 'set tdesc filename ....' to load a target description to which I have manually added the vector feature. This has shown that the vector register feature can be successfully parsed, and that the registers show up in the expected register groups. Additionally, the RISC-V vector extension is currently at v0.10, which is also the v1.0 draft release. However, this extension is not yet finalised. It is possible (but unlikely I think) that the register set could change between now and the final release of the vector extension. If this were to happen then we would potentially end up changing the requirements for the new org.gnu.gdb.riscv.vector feature. I really don't think it is likely that the register set will change this late in the process, and even if it did, changing the feature requirements will not be a problem as far as I am concerned (when the alternative is GDB just continues without this feature for now). gdb/ChangeLog: * NEWS: Mention new target feature name. * arch/riscv.c (riscv_create_target_description): GDB doesn't currently create target descriptions containing vector registers. * arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member variable. <operator==>: Also compare vlen. <hash>: Also include vlen. * riscv-tdep.c (riscv_feature_name_vector): New static global. (struct riscv_vector_feature): New struct. (riscv_vector_feature): New static global. (riscv_register_reggroup_p): Ensure vector registers are part of the 'all' group, and part of the 'vector' group. (riscv_dwarf_reg_to_regnum): Handle vector registers. (riscv_gdbarch_init): Check vector register feature. * riscv-tdep.h: Add vector registers to GDB's internal register numbers, and to the DWARF register numbers. gdb/doc/ChangeLog: * gdb.texinfo (RISC-V Features): Mention vector register feature.
137 lines
4.1 KiB
C
137 lines
4.1 KiB
C
/* Copyright (C) 2018-2021 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "gdbsupport/common-defs.h"
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#include "riscv.h"
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#include <stdlib.h>
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#include <unordered_map>
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#include "../features/riscv/32bit-cpu.c"
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#include "../features/riscv/64bit-cpu.c"
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#include "../features/riscv/32bit-fpu.c"
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#include "../features/riscv/64bit-fpu.c"
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#include "../features/riscv/rv32e-xregs.c"
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#ifndef GDBSERVER
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#define STATIC_IN_GDB static
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#else
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#define STATIC_IN_GDB
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#endif
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/* See arch/riscv.h. */
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STATIC_IN_GDB target_desc_up
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riscv_create_target_description (const struct riscv_gdbarch_features features)
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{
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/* Now we should create a new target description. */
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target_desc_up tdesc = allocate_target_description ();
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#ifndef IN_PROCESS_AGENT
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std::string arch_name = "riscv";
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if (features.xlen == 4)
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{
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if (features.embedded)
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arch_name.append (":rv32e");
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else
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arch_name.append (":rv32i");
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}
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else if (features.xlen == 8)
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arch_name.append (":rv64i");
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else if (features.xlen == 16)
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arch_name.append (":rv128i");
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if (features.flen == 4)
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arch_name.append ("f");
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else if (features.flen == 8)
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arch_name.append ("d");
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else if (features.flen == 16)
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arch_name.append ("q");
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set_tdesc_architecture (tdesc.get (), arch_name.c_str ());
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#endif
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long regnum = 0;
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/* For now we only support creating 32-bit or 64-bit x-registers. */
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if (features.xlen == 4)
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{
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if (features.embedded)
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regnum = create_feature_riscv_rv32e_xregs (tdesc.get (), regnum);
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else
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regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum);
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}
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else if (features.xlen == 8)
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regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum);
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/* For now we only support creating 32-bit or 64-bit f-registers. */
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if (features.flen == 4)
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regnum = create_feature_riscv_32bit_fpu (tdesc.get (), regnum);
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else if (features.flen == 8)
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regnum = create_feature_riscv_64bit_fpu (tdesc.get (), regnum);
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/* Currently GDB only supports vector features coming from remote
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targets. We don't support creating vector features on native targets
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(yet). */
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if (features.vlen != 0)
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error (_("unable to create vector feature"));
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return tdesc;
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}
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#ifndef GDBSERVER
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/* Wrapper used by std::unordered_map to generate hash for feature set. */
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struct riscv_gdbarch_features_hasher
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{
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std::size_t
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operator() (const riscv_gdbarch_features &features) const noexcept
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{
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return features.hash ();
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}
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};
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/* Cache of previously seen target descriptions, indexed by the feature set
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that created them. */
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static std::unordered_map<riscv_gdbarch_features,
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const target_desc_up,
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riscv_gdbarch_features_hasher> riscv_tdesc_cache;
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/* See arch/riscv.h. */
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const target_desc *
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riscv_lookup_target_description (const struct riscv_gdbarch_features features)
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{
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/* Lookup in the cache. If we find it then return the pointer out of
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the target_desc_up (which is a unique_ptr). This is safe as the
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riscv_tdesc_cache will exist until GDB exits. */
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const auto it = riscv_tdesc_cache.find (features);
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if (it != riscv_tdesc_cache.end ())
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return it->second.get ();
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target_desc_up tdesc (riscv_create_target_description (features));
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/* Add to the cache, and return a pointer borrowed from the
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target_desc_up. This is safe as the cache (and the pointers
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contained within it) are not deleted until GDB exits. */
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target_desc *ptr = tdesc.get ();
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riscv_tdesc_cache.emplace (features, std::move (tdesc));
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return ptr;
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}
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#endif /* !GDBSERVER */
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