Bernd Edlinger d8e753b791 sim: riscv: Fix confusion with c.jal vs. c.addiw ... There was apparently a confusion which cpu model uses compressed JAL and which ADDIW. Fixed that in execute_c, case MATCH_C_JAL | MATCH_C_ADDIW. Fixes 3224e32fb8 ("sim: riscv: Add support for compressed integer instructions") Approved-By: Andrew Burgess <aburgess@redhat.com>		2024-04-15 11:04:07 +02:00
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erc32	sim/erc32: Rename EVENT_MAX -> MAX_EVENTS	2024-03-21 10:46:23 -06:00
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riscv	sim: riscv: Fix confusion with c.jal vs. c.addiw	2024-04-15 11:04:07 +02:00
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