mirror of
https://sourceware.org/git/binutils-gdb.git
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06c441ccef
2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
158 lines
3.3 KiB
ArmAsm
158 lines
3.3 KiB
ArmAsm
# mips64 specific r6 tests (non FPU)
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# mach: mips64r6
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# as: -mabi=eabi
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# ld: -N -Ttext=0x80010000 -Tdata=0x80020000
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# output: *\\npass\\n
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.include "testutils.inc"
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.include "utils-r6.inc"
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.data
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d0: .dword 0
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dval: .dword 0xaa55bb66cc77dd88
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d1: .dword 0xaaaabbbbccccdddd
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d2: .dword 256
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dlo: .dword 0xaabbbbccccdddd00
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dhi: .dword 0xffffffffffffffaa
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dhiu: .dword 0x00000000000000aa
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d3: .dword 0xffaaaabbbbccccde
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d4: .dword 0xffffffffffffffdd
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d5: .dword 0x00000000000000dd
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d6: .dword 0x00aaaabbbbccccdd
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d7: .dword 0xeeeeffff00001111
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d8: .dword 0xbbccccddddeeeeff
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d9: .dword 0x000000ddaaaabbbb
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d10: .dword 0x5555dddd3333bbbb
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d11: .dword 0x9999999999999999
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d12: .dword 56
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d13: .dword 8
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d14: .dword 57
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d15: .dword 0x000000ddaaaac98b
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d16: .dword 0xffffffffdead00dd
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d17: .dword 0xffffffffc0de0000
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d18: .dword 0x0000123400000000
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d19: .dword 0xffffabcddead00dd
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d20: .dword 0xc0de000000000000
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d21: .dword 0x8000abcddead00dd
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dmask:.dword 0xffffffffffff0000
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dval1: .word 0x1234abcd
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dval2: .word 0xffee0000
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dval3: .dword 0xffffffffffffffff
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.fill 240,1,0
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dval4: .dword 0x5555555555555555
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.fill 264,1,0
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dval5: .dword 0xaaaaaaaaaaaaaaaa
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.text
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setup
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.set noreorder
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.ent DIAG
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DIAG:
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writemsg "[1] Test DMUL"
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r6ck_2r dmul, 6, 5, 30
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r6ck_2r dmul, -7, 9, -63
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r6ck_2r dmul, -1, 1, -1
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r6ck_2dr dmul, d1, d2, dlo
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writemsg "[2] Test DMUH"
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r6ck_2r dmuh, 6, 5, 0
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r6ck_2r dmuh, -7, 9, 0xffffffffffffffff
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r6ck_2r dmuh, -1, 1, -1
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r6ck_2dr dmuh, d1, d2, dhi
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writemsg "[3] Test DMULU"
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r6ck_2r dmulu, 12, 10, 120
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r6ck_2r dmulu, -1, 1, -1
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r6ck_2dr dmulu, d1, d2, dlo
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writemsg "[4] Test DMUHU"
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r6ck_2r dmuhu, 12, 10, 0
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r6ck_2r dmuhu, -1, 1, 0
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r6ck_2dr dmuhu, d1, d2, dhiu
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writemsg "[5] Test DDIV"
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r6ck_2r ddiv, 10001, 10, 1000
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r6ck_2r ddiv, -123456, 560, -220
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r6ck_2dr ddiv, d1, d2, d3
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writemsg "[6] Test DMOD"
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r6ck_2r dmod, 10001, 10, 1
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r6ck_2r dmod, -123456, 560, 0xffffffffffffff00
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r6ck_2dr dmod, d1, d2, d4
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writemsg "[7] Test DDIVU"
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r6ck_2r ddivu, 9, 100, 0
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r6ck_2dr ddivu, d1, d2, d6
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writemsg "[8] Test DMODU"
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r6ck_2r dmodu, 9, 100, 9
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r6ck_2dr dmodu, d1, d2, d5
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writemsg "[9] Test DALIGN"
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r6ck_2dr1i dalign, d7, d1, 3, d8
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r6ck_2dr1i dalign, d1, d5, 4, d9
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writemsg "[10] Test DBITSWAP"
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r6ck_1dr dbitswap, d1, d10
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r6ck_1dr dbitswap, d11, d11
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writemsg "[11] Test DCLZ"
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r6ck_1dr dclz, d5, d12
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r6ck_1dr dclz, d6, d13
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writemsg "[12] Test DCLO"
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r6ck_1dr dclo, d5, d0
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r6ck_1dr dclo, dhi, d14
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writemsg "[13] Test DLSA"
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r6ck_2r1i dlsa, 0x82, 0x2000068, 4, 0x2000888
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r6ck_2dr1i dlsa, d5, d9, 4, d15
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writemsg "[14] Test DAUI"
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r6ck_1dr1i daui, d5, 0xdead, d16
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r6ck_1dr1i daui, d0, 0xc0de, d17
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writemsg "[15] Test DAHI"
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r6ck_0dr1i dahi, d0, 0x1234, d18
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r6ck_0dr1i dahi, d16, 0xabce, d19
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writemsg "[16] Test DATI"
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r6ck_0dr1i dati, d0, 0xc0de, d20
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r6ck_0dr1i dati, d19, 0x8001, d21
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writemsg "[17] Test LDPC"
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ld $5, dval
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nop
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ldpc $4, dval
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fp_assert $4, $5
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writemsg "[18] Test LWUPC"
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lwu $5, dval1
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lwupc $4, dval1
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fp_assert $4, $5
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lwu $5, dval2
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lwupc $4, dval2
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fp_assert $4, $5
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writemsg "[19] Test LLD"
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ld $5, dval3
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dla $3, dval4
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lld $4, -248($3)
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fp_assert $4, $5
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writemsg "[20] Test SCD"
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lld $4, -248($3)
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dli $4, 0xafaf
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scd $4, -248($3)
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ld $5, dval3
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dli $4, 0xafaf
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fp_assert $4, $5
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pass
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.end DIAG
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