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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
411 lines
7.6 KiB
Plaintext
411 lines
7.6 KiB
Plaintext
# frv testcase for cfckul $FCCi,$CCj_float,$CCi,$cond
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# mach: all
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.include "testutils.inc"
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start
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.global cfckul
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cfckul:
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x0 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x1 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x2 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x3 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x4 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x5 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x6 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x7 0
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cfckul fcc0,cc3,cc0,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x8 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x9 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xa 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xb 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xc 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xd 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xe 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xf 0
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cfckul fcc0,cc3,cc4,1
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x0 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x1 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x2 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x3 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x4 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x5 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x6 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x7 0
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cfckul fcc0,cc3,cc0,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x8 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x9 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xa 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xb 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xc 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xd 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xe 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xf 0
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cfckul fcc0,cc3,cc4,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x0 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x1 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x2 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x3 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x4 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x5 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x6 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x7 0
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cfckul fcc0,cc3,cc1,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x8 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x9 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xa 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1b9b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xb 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xc 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xd 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xe 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xf 0
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cfckul fcc0,cc3,cc5,0
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test_spr_immed 0x1bdb,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x0 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x1 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x2 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x3 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x4 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x5 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x6 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x7 0
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cfckul fcc0,cc3,cc1,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x8 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x9 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xa 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xb 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xc 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xd 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xe 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xf 0
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cfckul fcc0,cc3,cc5,1
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x0 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x1 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x2 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x3 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x4 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x5 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x6 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x7 0
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cfckul fcc0,cc3,cc2,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x8 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0x9 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xa 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xb 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xc 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xd 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xe 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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set_spr_immed 0x1b5b,cccr
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set_fcc 0xf 0
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cfckul fcc0,cc3,cc6,0
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test_spr_immed 0x1b1b,cccr
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pass
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