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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
130 lines
4.0 KiB
ArmAsm
130 lines
4.0 KiB
ArmAsm
# Verify sign extension behavior with simultaneous acc additions, and
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# verify that no ASTAT bits get changed as a result
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# mach: bfin
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#include "test.h"
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.include "testutils.inc"
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start
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dmm32 ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
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dmm32 A0.w, 0x589145b7;
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dmm32 A0.x, 0xffffffee;
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dmm32 A1.w, 0x0b247b05;
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dmm32 A1.x, 0x0000005a;
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imm32 R3, 0x1e414332;
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imm32 R4, 0x351715b7;
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R3 = A1.L + A1.H, R4 = A0.L + A0.H;
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checkreg R3, 0x00008629;
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checkreg R4, 0x00009e48;
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checkreg ASTAT, (0x60304880 | _AV1S | _AC0 | _AN | _AZ);
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dmm32 ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
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dmm32 A0.w, 0xb2c58001;
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dmm32 A0.x, 0x00000000;
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dmm32 A1.w, 0xe999dc28;
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dmm32 A1.x, 0xffffffff;
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imm32 R0, 0xe58d5ffa;
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imm32 R4, 0x7fff7fff;
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R0 = A1.L + A1.H, R4 = A0.L + A0.H;
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checkreg R0, 0xffffc5c1;
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checkreg R4, 0xffff32c6;
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checkreg ASTAT, (0x40e0cc00 | _VS | _V | _AV1S | _AV0S | _AC0 | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
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dmm32 A0.w, 0xeff48350;
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dmm32 A0.x, 0xffffffff;
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dmm32 A1.w, 0x5a3f623a;
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dmm32 A1.x, 0xffffffff;
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imm32 R4, 0xffff152f;
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imm32 R6, 0xdd13218a;
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R4 = A1.L + A1.H, R6 = A0.L + A0.H;
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checkreg R4, 0x0000bc79;
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checkreg R6, 0xffff7344;
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checkreg ASTAT, (0x3420ca80 | _VS | _AV0S | _AC1 | _AC0 | _AQ | _CC);
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dmm32 ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
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dmm32 A0.w, 0x6da679bb;
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dmm32 A0.x, 0xffffff96;
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dmm32 A1.w, 0x1f5fb024;
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dmm32 A1.x, 0x00000000;
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imm32 R3, 0x3ebf8000;
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imm32 R6, 0x025f2e8c;
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R6 = A1.L + A1.H, R3 = A0.L + A0.H;
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checkreg R3, 0x0000e761;
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checkreg R6, 0xffffcf83;
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checkreg ASTAT, (0x10204880 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AN);
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dmm32 ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
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dmm32 A0.w, 0x59abaa84;
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dmm32 A0.x, 0xffffffe1;
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dmm32 A1.w, 0x71541efe;
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dmm32 A1.x, 0x00000009;
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imm32 R0, 0x2c41e797;
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imm32 R5, 0x7bfa5e8a;
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R0 = A1.L + A1.H, R5 = A0.L + A0.H;
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checkreg R0, 0x00009052;
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checkreg R5, 0x0000042f;
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checkreg ASTAT, (0x6ca00c90 | _V | _AV1S | _AV1 | _AC0_COPY | _AN | _AZ);
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dmm32 ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
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dmm32 A0.w, 0xffffffff;
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dmm32 A0.x, 0xffffffff;
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dmm32 A1.w, 0xc49ca8db;
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dmm32 A1.x, 0xffffffff;
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imm32 R3, 0x0f62ffff;
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imm32 R4, 0x09505188;
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R4 = A1.L + A1.H, R3 = A0.L + A0.H;
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checkreg R3, 0xfffffffe;
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checkreg R4, 0xffff6d77;
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checkreg ASTAT, (0x1c50c290 | _VS | _AV0S | _AV0 | _AC1 | _AC0 | _AQ | _AN);
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dmm32 ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
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dmm32 A0.w, 0xd827823e;
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dmm32 A0.x, 0xffffffff;
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dmm32 A1.w, 0x303d11ba;
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dmm32 A1.x, 0x00000000;
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imm32 R1, 0x80007fff;
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imm32 R6, 0xffc4feb3;
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R6 = A1.L + A1.H, R1 = A0.L + A0.H;
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checkreg R1, 0xffff5a65;
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checkreg R6, 0x000041f7;
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checkreg ASTAT, (0x70e04a90 | _VS | _AV0S | _AQ);
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dmm32 ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
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dmm32 A0.w, 0x97049850;
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dmm32 A0.x, 0x00000000;
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dmm32 A1.w, 0xffffa014;
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dmm32 A1.x, 0xffffffff;
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imm32 R0, 0x04828378;
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imm32 R5, 0x3d9effff;
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R0 = A1.L + A1.H, R5 = A0.L + A0.H;
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checkreg R0, 0xffffa013;
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checkreg R5, 0xffff2f54;
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checkreg ASTAT, (0x5c80c200 | _VS | _AV0S | _AQ | _AC0_COPY | _AN);
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dmm32 ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
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dmm32 A0.w, 0xac43c455;
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dmm32 A0.x, 0x00000000;
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dmm32 A1.w, 0x03de6f39;
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dmm32 A1.x, 0x00000000;
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imm32 R0, 0x5bbfd2d1;
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imm32 R3, 0x22425ebc;
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R3 = A1.L + A1.H, R0 = A0.L + A0.H;
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checkreg R0, 0xffff7098;
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checkreg R3, 0x00007317;
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checkreg ASTAT, (0x6c604600 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AZ);
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dmm32 ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
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dmm32 A0.w, 0xb63ac8f5;
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dmm32 A0.x, 0xffffffe0;
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dmm32 A1.w, 0x358b94e8;
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dmm32 A1.x, 0x00000000;
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imm32 R1, 0x80007fff;
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imm32 R6, 0x4f4a8883;
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R6 = A1.L + A1.H, R1 = A0.L + A0.H;
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checkreg R1, 0xffff7f2f;
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checkreg R6, 0xffffca73;
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checkreg ASTAT, (0x7cd04280 | _VS | _V | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
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pass
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