mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
217 lines
3.4 KiB
ArmAsm
217 lines
3.4 KiB
ArmAsm
# mach: aarch64
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# Check the unzip instructions: uzp1, uzp2.
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.include "testutils.inc"
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.data
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.align 4
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input1:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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input2:
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.word 0x14131211
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.word 0x18171615
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.word 0x1c1b1a19
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.word 0x201f1e1d
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zl8b:
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.word 0x07050301
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.word 0x17151311
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zu8b:
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.word 0x08060402
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.word 0x18161412
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zl16b:
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.word 0x07050301
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.word 0x0f0d0b09
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.word 0x17151311
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.word 0x1f1d1b19
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zu16b:
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.word 0x08060402
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.word 0x100e0c0a
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.word 0x18161412
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.word 0x201e1c1a
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zl4h:
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.word 0x06050201
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.word 0x16151211
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zu4h:
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.word 0x08070403
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.word 0x18171413
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zl8h:
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.word 0x06050201
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.word 0x0e0d0a09
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.word 0x16151211
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.word 0x1e1d1a19
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zu8h:
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.word 0x08070403
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.word 0x100f0c0b
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.word 0x18171413
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.word 0x201f1c1b
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zl2s:
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.word 0x04030201
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.word 0x14131211
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zu2s:
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.word 0x08070605
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.word 0x18171615
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zl4s:
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.word 0x04030201
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.word 0x0c0b0a09
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.word 0x14131211
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.word 0x1c1b1a19
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zu4s:
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.word 0x08070605
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.word 0x100f0e0d
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.word 0x18171615
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.word 0x201f1e1d
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zl2d:
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.word 0x04030201
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.word 0x08070605
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.word 0x14131211
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.word 0x18171615
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zu2d:
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.word 0x0c0b0a09
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.word 0x100f0e0d
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.word 0x1c1b1a19
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.word 0x201f1e1d
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start
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adrp x0, input1
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ldr q0, [x0, #:lo12:input1]
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adrp x0, input2
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ldr q1, [x0, #:lo12:input2]
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uzp1 v2.8b, v0.8b, v1.8b
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mov x1, v2.d[0]
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adrp x3, zl8b
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ldr x4, [x3, #:lo12:zl8b]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.8b, v0.8b, v1.8b
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mov x1, v2.d[0]
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adrp x3, zu8b
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ldr x4, [x3, #:lo12:zu8b]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.16b, v0.16b, v1.16b
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl16b
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ldr x4, [x3, #:lo12:zl16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl16b+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.16b, v0.16b, v1.16b
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu16b
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ldr x4, [x3, #:lo12:zu16b]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu16b+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.4h, v0.4h, v1.4h
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mov x1, v2.d[0]
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adrp x3, zl4h
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ldr x4, [x3, #:lo12:zl4h]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.4h, v0.4h, v1.4h
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mov x1, v2.d[0]
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adrp x3, zu4h
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ldr x4, [x3, #:lo12:zu4h]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.8h, v0.8h, v1.8h
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl8h
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ldr x4, [x3, #:lo12:zl8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl8h+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.8h, v0.8h, v1.8h
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu8h
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ldr x4, [x3, #:lo12:zu8h]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu8h+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.2s, v0.2s, v1.2s
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mov x1, v2.d[0]
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adrp x3, zl2s
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ldr x4, [x3, #:lo12:zl2s]
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cmp x1, x4
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bne .Lfailure
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uzp2 v2.2s, v0.2s, v1.2s
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mov x1, v2.d[0]
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adrp x3, zu2s
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ldr x4, [x3, #:lo12:zu2s]
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cmp x1, x4
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bne .Lfailure
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uzp1 v2.4s, v0.4s, v1.4s
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl4s
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ldr x4, [x3, #:lo12:zl4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl4s+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.4s, v0.4s, v1.4s
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu4s
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ldr x4, [x3, #:lo12:zu4s]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu4s+8]
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cmp x2, x5
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bne .Lfailure
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uzp1 v2.2d, v0.2d, v1.2d
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zl2d
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ldr x4, [x3, #:lo12:zl2d]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zl2d+8]
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cmp x2, x5
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bne .Lfailure
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uzp2 v2.2d, v0.2d, v1.2d
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mov x1, v2.d[0]
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mov x2, v2.d[1]
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adrp x3, zu2d
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ldr x4, [x3, #:lo12:zu2d]
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cmp x1, x4
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bne .Lfailure
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ldr x5, [x3, #:lo12:zu2d+8]
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cmp x2, x5
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bne .Lfailure
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pass
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.Lfailure:
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fail
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