mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
204 lines
3.4 KiB
ArmAsm
204 lines
3.4 KiB
ArmAsm
# mach: aarch64
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# Check the FP convert to int round toward zero instructions: fcvtszs32,
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# fcvtszs, fcvtszd32, fcvtszd, fcvtzu.
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# For 32-bit signed convert, test values -1.5, INT_MAX, and INT_MIN.
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# For 64-bit signed convert, test values -1.5, LONG_MAX, and LONG_MIN.
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# For 32-bit unsigned convert, test values 1.5, INT_MAX, and UINT_MAX.
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# For 64-bit unsigned convert, test values 1.5, LONG_MAX, and ULONG_MAX.
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.data
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.align 4
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fm1p5:
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.word 3217031168
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fimax:
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.word 1325400064
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fimin:
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.word 3472883712
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flmax:
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.word 1593835520
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flmin:
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.word 3741319168
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f1p5:
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.word 1069547520
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fuimax:
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.word 1333788672
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fulmax:
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.word 1602224128
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dm1p5:
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.word 0
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.word -1074266112
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dimax:
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.word 4290772992
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.word 1105199103
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dimin:
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.word 0
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.word -1042284544
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dlmax:
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.word 0
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.word 1138753536
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dlmin:
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.word 0
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.word -1008730112
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d1p5:
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.word 0
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.word 1073217536
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duimax:
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.word 4292870144
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.word 1106247679
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dulmax:
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.word 0
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.word 1139802112
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.include "testutils.inc"
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start
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adrp x0, fm1p5
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ldr s0, [x0, #:lo12:fm1p5]
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fcvtzs w1, s0
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cmp w1, #-1
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bne .Lfailure
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adrp x0, fimax
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ldr s0, [x0, #:lo12:fimax]
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fcvtzs w1, s0
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mov w2, #0x7fffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, fimin
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ldr s0, [x0, #:lo12:fimin]
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fcvtzs w1, s0
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mov w2, #0x80000000
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cmp w1, w2
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bne .Lfailure
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adrp x0, fm1p5
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ldr s0, [x0, #:lo12:fm1p5]
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fcvtzs x1, s0
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cmp x1, #-1
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bne .Lfailure
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adrp x0, flmax
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ldr s0, [x0, #:lo12:flmax]
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fcvtzs x1, s0
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mov x2, #0x7fffffffffffffff
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cmp x1, x2
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bne .Lfailure
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adrp x0, flmin
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ldr s0, [x0, #:lo12:flmin]
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fcvtzs x1, s0
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mov x2, #0x8000000000000000
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cmp x1, x2
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bne .Lfailure
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adrp x0, dm1p5
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ldr d0, [x0, #:lo12:dm1p5]
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fcvtzs w1, d0
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cmp w1, #-1
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bne .Lfailure
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adrp x0, dimax
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ldr d0, [x0, #:lo12:dimax]
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fcvtzs w1, d0
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mov w2, #0x7fffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, dimin
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ldr d0, [x0, #:lo12:dimin]
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fcvtzs w1, d0
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mov w2, #0x80000000
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cmp w1, w2
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bne .Lfailure
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adrp x0, dm1p5
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ldr d0, [x0, #:lo12:dm1p5]
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fcvtzs x1, d0
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cmp x1, #-1
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bne .Lfailure
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adrp x0, dlmax
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ldr d0, [x0, #:lo12:dlmax]
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fcvtzs x1, d0
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mov x2, #0x7fffffffffffffff
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cmp x1, x2
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bne .Lfailure
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adrp x0, dlmin
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ldr d0, [x0, #:lo12:dlmin]
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fcvtzs x1, d0
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mov x2, #0x8000000000000000
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cmp x1, x2
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bne .Lfailure
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adrp x0, f1p5
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ldr s0, [x0, #:lo12:f1p5]
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fcvtzu w1, s0
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cmp w1, #1
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bne .Lfailure
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adrp x0, fimax
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ldr s0, [x0, #:lo12:fimax]
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fcvtzu w1, s0
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mov w2, #0x80000000
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cmp w1, w2
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bne .Lfailure
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adrp x0, fuimax
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ldr s0, [x0, #:lo12:fuimax]
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fcvtzu w1, s0
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mov w2, #0xffffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, f1p5
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ldr s0, [x0, #:lo12:f1p5]
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fcvtzu x1, s0
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cmp x1, #1
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bne .Lfailure
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adrp x0, flmax
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ldr s0, [x0, #:lo12:flmax]
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fcvtzu x1, s0
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mov x2, #0x8000000000000000
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cmp x1, x2
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bne .Lfailure
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adrp x0, fulmax
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ldr s0, [x0, #:lo12:fulmax]
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fcvtzu x1, s0
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mov x2, #0xffffffffffffffff
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cmp x1, x2
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bne .Lfailure
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adrp x0, d1p5
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ldr d0, [x0, #:lo12:d1p5]
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fcvtzu w1, d0
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cmp w1, #1
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bne .Lfailure
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adrp x0, dimax
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ldr d0, [x0, #:lo12:dimax]
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fcvtzu w1, d0
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mov w2, #0x7fffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, duimax
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ldr d0, [x0, #:lo12:duimax]
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fcvtzu w1, d0
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mov w2, #0xffffffff
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cmp w1, w2
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bne .Lfailure
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adrp x0, d1p5
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ldr d0, [x0, #:lo12:d1p5]
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fcvtzu x1, d0
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cmp x1, #1
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bne .Lfailure
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adrp x0, dlmax
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ldr d0, [x0, #:lo12:dlmax]
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fcvtzu x1, d0
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mov x2, #0x8000000000000000
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cmp x1, x2
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bne .Lfailure
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adrp x0, dulmax
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ldr d0, [x0, #:lo12:dulmax]
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fcvtzu x1, d0
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mov x2, #0xffffffffffffffff
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cmp x1, x2
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bne .Lfailure
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pass
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.Lfailure:
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fail
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