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24b368f853
gas * config/tc-arc.c (arc_option): Sets all internal gas options when parsing .cpu directive. (declare_register_set): Declare all 64 registers. (md_section_align): Refactor. (md_pcrel_from_section): Remove assert. (pseudo_operand_match): Fix pseudo operand match. (find_reloc): Use flags filed, extend matching. * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT relocation. testsuite * gas/arc/bic.d: Update test. * gas/arc/add_s-err.s: New file. * gas/arc/cpu-warn1.s: Likewise. * gas/arc/pcl-relocs.d: Likewise. * gas/arc/pcl-relocs.s: Likewise. * gas/arc/pcrel-relocs.d: Likewise. * gas/arc/pcrel-relocs.s: Likewise. * gas/arc/pic-relocs.d: Likewise. * gas/arc/pic-relocs.s: Likewise. * gas/arc/plt-relocs.d: Likewise. * gas/arc/plt-relocs.s: Likewise. * gas/arc/pseudos.d: Likewise. * gas/arc/pseudos.s: Likewise. * gas/arc/sda-relocs.d: Likewise. * gas/arc/sda-relocs.s: Likewise. * gas/arc/sda-relocs2.d: Likewise. * gas/arc/sda-relocs2.s: Likewise. * gas/arc/tls-relocs.d: Likewise. * gas/arc/tls-relocs.s: Likewise. opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. opcodes * arc-dis.c (special_flag_p): Match full mnemonic. * arc-opc.c (print_insn_arc): Check section size to read appropriate number of bytes. Fix printing. * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without arguments.
592 lines
15 KiB
C
592 lines
15 KiB
C
/* Instruction printing code for the ARC.
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Copyright (C) 1994-2015 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include <assert.h>
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#include "dis-asm.h"
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#include "opcode/arc.h"
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#include "arc-dis.h"
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#include "arc-ext.h"
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/* Globals variables. */
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static const char * const regnames[64] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
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"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
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"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
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"r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
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"r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
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};
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/* Macros section. */
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#ifdef DEBUG
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# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
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#else
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# define pr_debug(fmt, args...)
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#endif
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#define ARRANGE_ENDIAN(info, buf) \
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(info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
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: bfd_getb32 (buf))
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#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
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(s + (sizeof (word) * 8 - 1 - e)))
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#define OPCODE(word) (BITS ((word), 27, 31))
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#define FIELDA(word) (BITS ((word), 21, 26))
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#define FIELDB(word) (BITS ((word), 15, 20))
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#define FIELDC(word) (BITS ((word), 9, 14))
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#define OPCODE_AC(word) (BITS ((word), 11, 15))
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/* Functions implementation. */
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static bfd_vma
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bfd_getm32 (unsigned int data)
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{
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bfd_vma value = 0;
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value = ((data & 0xff00) | (data & 0xff)) << 16;
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value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
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return value;
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}
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static int
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special_flag_p (const char *opname,
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const char *flgname)
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{
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const struct arc_flag_special *flg_spec;
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unsigned i, j, flgidx;
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for (i = 0; i < arc_num_flag_special; i++)
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{
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flg_spec = &arc_flag_special_cases[i];
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if (strcmp (opname, flg_spec->name))
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continue;
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/* Found potential special case instruction. */
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for (j=0;; ++j)
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{
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flgidx = flg_spec->flags[j];
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if (flgidx == 0)
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break; /* End of the array. */
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if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
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return 1;
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}
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}
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return 0;
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}
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/* Disassemble ARC instructions. */
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static int
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print_insn_arc (bfd_vma memaddr,
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struct disassemble_info *info)
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{
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bfd_byte buffer[4];
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unsigned int lowbyte, highbyte;
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int status;
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unsigned int i;
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int insnLen = 0;
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unsigned insn[2] = { 0, 0 };
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unsigned isa_mask;
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const unsigned char *opidx;
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const unsigned char *flgidx;
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const struct arc_opcode *opcode;
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const char *instrName;
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int flags;
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bfd_boolean need_comma;
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bfd_boolean open_braket;
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int size;
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lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
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highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
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switch (info->mach)
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{
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case bfd_mach_arc_arc700:
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isa_mask = ARC_OPCODE_ARC700;
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break;
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case bfd_mach_arc_arc600:
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isa_mask = ARC_OPCODE_ARC600;
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break;
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case bfd_mach_arc_arcv2:
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default:
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isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
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break;
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}
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/* This variable may be set by the instruction decoder. It suggests
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the number of bytes objdump should display on a single line. If
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the instruction decoder sets this, it should always set it to
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the same value in order to get reasonable looking output. */
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info->bytes_per_line = 8;
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/* In the next lines, we set two info variables control the way
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objdump displays the raw data. For example, if bytes_per_line is
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8 and bytes_per_chunk is 4, the output will look like this:
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00: 00000000 00000000
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with the chunks displayed according to "display_endian". */
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if (info->section
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&& !(info->section->flags & SEC_CODE))
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{
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/* This is not a CODE section. */
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switch (info->section->size)
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{
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case 1:
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case 2:
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case 4:
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size = info->section->size;
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break;
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default:
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size = (info->section->size & 0x01) ? 1 : 4;
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break;
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}
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info->bytes_per_chunk = 1;
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info->display_endian = info->endian;
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}
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else
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{
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size = 2;
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info->bytes_per_chunk = 2;
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info->display_endian = info->endian;
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}
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/* Read the insn into a host word. */
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status = (*info->read_memory_func) (memaddr, buffer, size, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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if (info->section
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&& !(info->section->flags & SEC_CODE))
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{
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/* Data section. */
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unsigned long data;
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data = bfd_get_bits (buffer, size * 8,
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info->display_endian == BFD_ENDIAN_BIG);
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switch (size)
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{
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case 1:
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(*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
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break;
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case 2:
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(*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
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break;
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case 4:
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(*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
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break;
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default:
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abort ();
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}
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return size;
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}
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if ( (((buffer[lowbyte] & 0xf8) > 0x38)
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&& ((buffer[lowbyte] & 0xf8) != 0x48))
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|| ((info->mach == bfd_mach_arc_arcv2)
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&& ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly. */
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)
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{
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/* This is a short instruction. */
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insnLen = 2;
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insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
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}
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else
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{
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insnLen = 4;
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/* This is a long instruction: Read the remaning 2 bytes. */
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status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr + 2, info);
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return -1;
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}
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insn[0] = ARRANGE_ENDIAN (info, buffer);
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}
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/* Set some defaults for the insn info. */
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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info->data_size = 0;
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info->insn_type = dis_nonbranch;
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info->target = 0;
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info->target2 = 0;
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/* FIXME to be moved in dissasemble_init_for_target. */
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info->disassembler_needs_relocs = TRUE;
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/* Find the first match in the opcode table. */
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for (i = 0; i < arc_num_opcodes; i++)
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{
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bfd_boolean invalid = FALSE;
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opcode = &arc_opcodes[i];
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if (ARC_SHORT (opcode->mask) && (insnLen == 2))
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{
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if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
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continue;
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}
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else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
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{
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if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
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continue;
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}
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else
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continue;
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if ((insn[0] ^ opcode->opcode) & opcode->mask)
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continue;
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if (!(opcode->cpu & isa_mask))
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continue;
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/* Possible candidate, check the operands. */
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for (opidx = opcode->operands; *opidx; opidx++)
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{
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int value;
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const struct arc_operand *operand = &arc_operands[*opidx];
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if (operand->flags & ARC_OPERAND_FAKE)
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continue;
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if (operand->extract)
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value = (*operand->extract) (insn[0], &invalid);
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else
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
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/* Check for LIMM indicator. If it is there, then make sure
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we pick the right format. */
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if (operand->flags & ARC_OPERAND_IR
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&& !(operand->flags & ARC_OPERAND_LIMM))
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{
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if ((value == 0x3E && insnLen == 4)
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|| (value == 0x1E && insnLen == 2))
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{
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invalid = TRUE;
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break;
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}
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}
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}
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/* Check the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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int foundA = 0, foundB = 0;
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
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unsigned int value;
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value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
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if (value == flg_operand->code)
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foundA = 1;
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if (value)
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foundB = 1;
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}
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if (!foundA && foundB)
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{
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invalid = TRUE;
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break;
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}
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}
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if (invalid)
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continue;
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/* The instruction is valid. */
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goto found;
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}
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/* No instruction found. Try the extenssions. */
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instrName = arcExtMap_instName (OPCODE (insn[0]), insn[0], &flags);
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if (instrName)
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{
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opcode = &arc_opcodes[0];
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(*info->fprintf_func) (info->stream, "%s", instrName);
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goto print_flags;
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}
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if (insnLen == 2)
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(*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
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else
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(*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
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info->insn_type = dis_noninsn;
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return insnLen;
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found:
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/* Print the mnemonic. */
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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/* Preselect the insn class. */
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switch (opcode->class)
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{
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case BRANCH:
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case JUMP:
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if (!strncmp (opcode->name, "bl", 2)
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|| !strncmp (opcode->name, "jl", 2))
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info->insn_type = dis_jsr;
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else
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info->insn_type = dis_branch;
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break;
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case MEMORY:
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info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
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break;
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default:
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info->insn_type = dis_nonbranch;
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break;
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}
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pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
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print_flags:
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/* Now extract and print the flags. */
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for (flgidx = opcode->flags; *flgidx; flgidx++)
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{
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/* Get a valid flag class. */
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const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
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const unsigned *flgopridx;
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for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
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{
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const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
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unsigned int value;
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if (!flg_operand->favail)
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continue;
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value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
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if (value == flg_operand->code)
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{
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/* FIXME!: print correctly nt/t flag. */
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if (!special_flag_p (opcode->name, flg_operand->name))
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(*info->fprintf_func) (info->stream, ".");
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else if (info->insn_type == dis_dref)
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{
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switch (flg_operand->name[0])
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{
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case 'b':
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info->data_size = 1;
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break;
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case 'h':
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case 'w':
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info->data_size = 2;
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break;
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default:
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info->data_size = 4;
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break;
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}
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}
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(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
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}
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if (flg_operand->name[0] == 'd'
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&& flg_operand->name[1] == 0)
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info->branch_delay_insns = 1;
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}
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}
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if (opcode->operands[0] != 0)
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(*info->fprintf_func) (info->stream, "\t");
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need_comma = FALSE;
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open_braket = FALSE;
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/* Now extract and print the operands. */
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for (opidx = opcode->operands; *opidx; opidx++)
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{
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const struct arc_operand *operand = &arc_operands[*opidx];
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int value;
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if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
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{
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(*info->fprintf_func) (info->stream, "]");
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open_braket = FALSE;
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continue;
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}
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/* Only take input from real operands. */
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if ((operand->flags & ARC_OPERAND_FAKE)
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&& !(operand->flags & ARC_OPERAND_BRAKET))
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continue;
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if (operand->extract)
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value = (*operand->extract) (insn[0], (int *) NULL);
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else
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{
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if (operand->flags & ARC_OPERAND_ALIGNED32)
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{
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value = (insn[0] >> operand->shift)
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& ((1 << (operand->bits - 2)) - 1);
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value = value << 2;
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}
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else
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{
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value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
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}
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if (operand->flags & ARC_OPERAND_SIGNED)
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{
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int signbit = 1 << (operand->bits - 1);
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value = (value ^ signbit) - signbit;
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}
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}
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if (operand->flags & ARC_OPERAND_IGNORE
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&& (operand->flags & ARC_OPERAND_IR
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&& value == -1))
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continue;
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if (need_comma)
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(*info->fprintf_func) (info->stream, ",");
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if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
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{
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(*info->fprintf_func) (info->stream, "[");
|
|
open_braket = TRUE;
|
|
need_comma = FALSE;
|
|
continue;
|
|
}
|
|
|
|
/* Read the limm operand, if required. */
|
|
if (operand->flags & ARC_OPERAND_LIMM
|
|
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
|
|
{
|
|
status = (*info->read_memory_func) (memaddr + insnLen, buffer,
|
|
4, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, memaddr + insnLen, info);
|
|
return -1;
|
|
}
|
|
insn[1] = ARRANGE_ENDIAN (info, buffer);
|
|
}
|
|
|
|
/* Print the operand as directed by the flags. */
|
|
if (operand->flags & ARC_OPERAND_IR)
|
|
{
|
|
assert (value >=0 && value < 64);
|
|
(*info->fprintf_func) (info->stream, "%s", regnames[value]);
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE)
|
|
(*info->fprintf_func) (info->stream, "%s", regnames[value+1]);
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_LIMM)
|
|
{
|
|
(*info->fprintf_func) (info->stream, "%#x", insn[1]);
|
|
if (info->insn_type == dis_branch
|
|
|| info->insn_type == dis_jsr)
|
|
info->target = (bfd_vma) insn[1];
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_PCREL)
|
|
{
|
|
/* PCL relative. */
|
|
if (info->flags & INSN_HAS_RELOC)
|
|
memaddr = 0;
|
|
(*info->print_address_func) ((memaddr & ~3) + value, info);
|
|
|
|
info->target = (bfd_vma) (memaddr & ~3) + value;
|
|
}
|
|
else if (operand->flags & ARC_OPERAND_SIGNED)
|
|
(*info->fprintf_func) (info->stream, "%d", value);
|
|
else
|
|
if (operand->flags & ARC_OPERAND_TRUNCATE
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED32)
|
|
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
|
|
&& value > 0 && value <= 14)
|
|
(*info->fprintf_func) (info->stream, "r13-%s",
|
|
regnames[13 + value - 1]);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%#x", value);
|
|
|
|
need_comma = TRUE;
|
|
|
|
/* Adjust insn len. */
|
|
if (operand->flags & ARC_OPERAND_LIMM
|
|
&& !(operand->flags & ARC_OPERAND_DUPLICATE))
|
|
insnLen += 4;
|
|
}
|
|
|
|
return insnLen;
|
|
}
|
|
|
|
|
|
disassembler_ftype
|
|
arc_get_disassembler (bfd *abfd)
|
|
{
|
|
/* Read the extenssion insns and registers, if any. */
|
|
build_ARC_extmap (abfd);
|
|
dump_ARC_extmap ();
|
|
|
|
return print_insn_arc;
|
|
}
|
|
|
|
/* Disassemble ARC instructions. Used by debugger. */
|
|
|
|
struct arcDisState
|
|
arcAnalyzeInstr (bfd_vma memaddr,
|
|
struct disassemble_info *info)
|
|
{
|
|
struct arcDisState ret;
|
|
memset (&ret, 0, sizeof (struct arcDisState));
|
|
|
|
ret.instructionLen = print_insn_arc (memaddr, info);
|
|
|
|
#if 0
|
|
ret.words[0] = insn[0];
|
|
ret.words[1] = insn[1];
|
|
ret._this = &ret;
|
|
ret.coreRegName = _coreRegName;
|
|
ret.auxRegName = _auxRegName;
|
|
ret.condCodeName = _condCodeName;
|
|
ret.instName = _instName;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Local variables:
|
|
eval: (c-set-style "gnu")
|
|
indent-tabs-mode: t
|
|
End: */
|