mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
3666a04883
This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
159 lines
6.7 KiB
XML
159 lines
6.7 KiB
XML
<?xml version="1.0"?>
|
|
<!-- Copyright (C) 2009-2021 Free Software Foundation, Inc.
|
|
Contributed by ARM Ltd.
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
are permitted in any medium without royalty provided the copyright
|
|
notice and this notice are preserved. -->
|
|
|
|
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
|
|
<feature name="org.gnu.gdb.aarch64.fpu">
|
|
<vector id="v2d" type="ieee_double" count="2"/>
|
|
<vector id="v2u" type="uint64" count="2"/>
|
|
<vector id="v2i" type="int64" count="2"/>
|
|
<vector id="v4f" type="ieee_single" count="4"/>
|
|
<vector id="v4u" type="uint32" count="4"/>
|
|
<vector id="v4i" type="int32" count="4"/>
|
|
<vector id="v8f" type="ieee_half" count="8"/>
|
|
<vector id="v8u" type="uint16" count="8"/>
|
|
<vector id="v8i" type="int16" count="8"/>
|
|
<vector id="v16u" type="uint8" count="16"/>
|
|
<vector id="v16i" type="int8" count="16"/>
|
|
<vector id="v1u" type="uint128" count="1"/>
|
|
<vector id="v1i" type="int128" count="1"/>
|
|
<union id="vnd">
|
|
<field name="f" type="v2d"/>
|
|
<field name="u" type="v2u"/>
|
|
<field name="s" type="v2i"/>
|
|
</union>
|
|
<union id="vns">
|
|
<field name="f" type="v4f"/>
|
|
<field name="u" type="v4u"/>
|
|
<field name="s" type="v4i"/>
|
|
</union>
|
|
<union id="vnh">
|
|
<field name="f" type="v8f"/>
|
|
<field name="u" type="v8u"/>
|
|
<field name="s" type="v8i"/>
|
|
</union>
|
|
<union id="vnb">
|
|
<field name="u" type="v16u"/>
|
|
<field name="s" type="v16i"/>
|
|
</union>
|
|
<union id="vnq">
|
|
<field name="u" type="v1u"/>
|
|
<field name="s" type="v1i"/>
|
|
</union>
|
|
<union id="aarch64v">
|
|
<field name="d" type="vnd"/>
|
|
<field name="s" type="vns"/>
|
|
<field name="h" type="vnh"/>
|
|
<field name="b" type="vnb"/>
|
|
<field name="q" type="vnq"/>
|
|
</union>
|
|
<reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
|
|
<reg name="v1" bitsize="128" type="aarch64v" />
|
|
<reg name="v2" bitsize="128" type="aarch64v" />
|
|
<reg name="v3" bitsize="128" type="aarch64v" />
|
|
<reg name="v4" bitsize="128" type="aarch64v" />
|
|
<reg name="v5" bitsize="128" type="aarch64v" />
|
|
<reg name="v6" bitsize="128" type="aarch64v" />
|
|
<reg name="v7" bitsize="128" type="aarch64v" />
|
|
<reg name="v8" bitsize="128" type="aarch64v" />
|
|
<reg name="v9" bitsize="128" type="aarch64v" />
|
|
<reg name="v10" bitsize="128" type="aarch64v"/>
|
|
<reg name="v11" bitsize="128" type="aarch64v"/>
|
|
<reg name="v12" bitsize="128" type="aarch64v"/>
|
|
<reg name="v13" bitsize="128" type="aarch64v"/>
|
|
<reg name="v14" bitsize="128" type="aarch64v"/>
|
|
<reg name="v15" bitsize="128" type="aarch64v"/>
|
|
<reg name="v16" bitsize="128" type="aarch64v"/>
|
|
<reg name="v17" bitsize="128" type="aarch64v"/>
|
|
<reg name="v18" bitsize="128" type="aarch64v"/>
|
|
<reg name="v19" bitsize="128" type="aarch64v"/>
|
|
<reg name="v20" bitsize="128" type="aarch64v"/>
|
|
<reg name="v21" bitsize="128" type="aarch64v"/>
|
|
<reg name="v22" bitsize="128" type="aarch64v"/>
|
|
<reg name="v23" bitsize="128" type="aarch64v"/>
|
|
<reg name="v24" bitsize="128" type="aarch64v"/>
|
|
<reg name="v25" bitsize="128" type="aarch64v"/>
|
|
<reg name="v26" bitsize="128" type="aarch64v"/>
|
|
<reg name="v27" bitsize="128" type="aarch64v"/>
|
|
<reg name="v28" bitsize="128" type="aarch64v"/>
|
|
<reg name="v29" bitsize="128" type="aarch64v"/>
|
|
<reg name="v30" bitsize="128" type="aarch64v"/>
|
|
<reg name="v31" bitsize="128" type="aarch64v"/>
|
|
|
|
<flags id="fpsr_flags" size="4">
|
|
<!-- Invalid Operation cumulative floating-point exception bit. -->
|
|
<field name="IOC" start="0" end="0"/>
|
|
<!-- Divide by Zero cumulative floating-point exception bit. -->
|
|
<field name="DZC" start="1" end="1"/>
|
|
<!-- Overflow cumulative floating-point exception bit. -->
|
|
<field name="OFC" start="2" end="2"/>
|
|
<!-- Underflow cumulative floating-point exception bit. -->
|
|
<field name="UFC" start="3" end="3"/>
|
|
<!-- Inexact cumulative floating-point exception bit.. -->
|
|
<field name="IXC" start="4" end="4"/>
|
|
<!-- Input Denormal cumulative floating-point exception bit. -->
|
|
<field name="IDC" start="7" end="7"/>
|
|
<!-- Cumulative saturation bit, Advanced SIMD only. -->
|
|
<field name="QC" start="27" end="27"/>
|
|
<!-- When AArch32 is supported at any Exception level and AArch32
|
|
floating-point is implemented: Overflow condition flag for AArch32
|
|
floating-point comparison operations. -->
|
|
<field name="V" start="28" end="28"/>
|
|
<!-- When AArch32 is supported at any Exception level and AArch32
|
|
floating-point is implemented:
|
|
Carry condition flag for AArch32 floating-point comparison operations.
|
|
-->
|
|
<field name="C" start="29" end="29"/>
|
|
<!-- When AArch32 is supported at any Exception level and AArch32
|
|
floating-point is implemented:
|
|
Zero condition flag for AArch32 floating-point comparison operations.
|
|
-->
|
|
<field name="Z" start="30" end="30"/>
|
|
<!-- When AArch32 is supported at any Exception level and AArch32
|
|
floating-point is implemented:
|
|
Negative condition flag for AArch32 floating-point comparison
|
|
operations. -->
|
|
<field name="N" start="31" end="31"/>
|
|
</flags>
|
|
<reg name="fpsr" bitsize="32" type="fpsr_flags"/>
|
|
|
|
<flags id="fpcr_flags" size="4">
|
|
<!-- Flush Inputs to Zero (part of Armv8.7). -->
|
|
<field name="FIZ" start="0" end="0"/>
|
|
<!-- Alternate Handling (part of Armv8.7). -->
|
|
<field name="AH" start="1" end="1"/>
|
|
<!-- Controls how the output elements other than the lowest element of the
|
|
vector are determined for Advanced SIMD scalar instructions (part of
|
|
Armv8.7). -->
|
|
<field name="NEP" start="2" end="2"/>
|
|
<!-- Invalid Operation floating-point exception trap enable. -->
|
|
<field name="IOE" start="8" end="8"/>
|
|
<!-- Divide by Zero floating-point exception trap enable. -->
|
|
<field name="DZE" start="9" end="9"/>
|
|
<!-- Overflow floating-point exception trap enable. -->
|
|
<field name="OFE" start="10" end="10"/>
|
|
<!-- Underflow floating-point exception trap enable. -->
|
|
<field name="UFE" start="11" end="11"/>
|
|
<!-- Inexact floating-point exception trap enable. -->
|
|
<field name="IXE" start="12" end="12"/>
|
|
<!-- Input Denormal floating-point exception trap enable. -->
|
|
<field name="IDE" start="15" end="15"/>
|
|
<!-- Flush-to-zero mode control bit on half-precision data-processing
|
|
instructions. -->
|
|
<field name="FZ16" start="19" end="19"/>
|
|
<!-- Rounding Mode control field. -->
|
|
<field name="RMode" start="22" end="23"/>
|
|
<!-- Flush-to-zero mode control bit. -->
|
|
<field name="FZ" start="24" end="24"/>
|
|
<!-- Default NaN mode control bit. -->
|
|
<field name="DN" start="25" end="25"/>
|
|
<!-- Alternative half-precision control bit. -->
|
|
<field name="AHP" start="26" end="26"/>
|
|
</flags>
|
|
<reg name="fpcr" bitsize="32" type="fpcr_flags"/>
|
|
</feature>
|