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49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* Handle cache related addresses.
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Copyright (C) 1996-2018 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions and Mike Frysinger.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DV_M32R_CACHE_H
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#define DV_M32R_CACHE_H
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/* Support for the MSPR register (Cache Purge Control Register)
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and the MCCR register (Cache Control Register) are needed in order for
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overlays to work correctly with the scache.
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MSPR no longer exists but is supported for upward compatibility with
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early overlay support. */
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/* Cache Purge Control (only exists on early versions of chips) */
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#define MSPR_ADDR 0xfffffff7
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#define MSPR_PURGE 1
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/* Lock Control Register (not supported) */
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#define MLCR_ADDR 0xfffffff7
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#define MLCR_LM 1
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/* Power Management Control Register (not supported) */
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#define MPMR_ADDR 0xfffffffb
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/* Cache Control Register */
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#define MCCR_ADDR 0xffffffff
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#define MCCR_CP 0x80
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/* not supported */
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#define MCCR_CM0 2
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#define MCCR_CM1 1
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#endif
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