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https://sourceware.org/git/binutils-gdb.git
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d87bef3a7b
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/* This file defines the interface between the RISC-V simulator and GDB.
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Copyright (C) 2005-2023 Free Software Foundation, Inc.
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Contributed by Mike Frysinger.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* Order has to match gdb riscv-tdep list. */
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enum sim_riscv_regnum {
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SIM_RISCV_ZERO_REGNUM = 0,
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SIM_RISCV_RA_REGNUM,
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SIM_RISCV_SP_REGNUM,
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SIM_RISCV_GP_REGNUM,
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SIM_RISCV_TP_REGNUM,
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SIM_RISCV_T0_REGNUM,
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SIM_RISCV_T1_REGNUM,
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SIM_RISCV_T2_REGNUM,
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SIM_RISCV_S0_REGNUM,
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#define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM
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SIM_RISCV_S1_REGNUM,
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SIM_RISCV_A0_REGNUM,
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SIM_RISCV_A1_REGNUM,
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SIM_RISCV_A2_REGNUM,
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SIM_RISCV_A3_REGNUM,
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SIM_RISCV_A4_REGNUM,
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SIM_RISCV_A5_REGNUM,
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SIM_RISCV_A6_REGNUM,
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SIM_RISCV_A7_REGNUM,
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SIM_RISCV_S2_REGNUM,
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SIM_RISCV_S3_REGNUM,
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SIM_RISCV_S4_REGNUM,
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SIM_RISCV_S5_REGNUM,
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SIM_RISCV_S6_REGNUM,
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SIM_RISCV_S7_REGNUM,
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SIM_RISCV_S8_REGNUM,
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SIM_RISCV_S9_REGNUM,
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SIM_RISCV_S10_REGNUM,
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SIM_RISCV_S11_REGNUM,
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SIM_RISCV_T3_REGNUM,
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SIM_RISCV_T4_REGNUM,
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SIM_RISCV_T5_REGNUM,
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SIM_RISCV_T6_REGNUM,
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SIM_RISCV_PC_REGNUM,
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SIM_RISCV_FT0_REGNUM,
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#define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM
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SIM_RISCV_FT1_REGNUM,
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SIM_RISCV_FT2_REGNUM,
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SIM_RISCV_FT3_REGNUM,
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SIM_RISCV_FT4_REGNUM,
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SIM_RISCV_FT5_REGNUM,
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SIM_RISCV_FT6_REGNUM,
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SIM_RISCV_FT7_REGNUM,
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SIM_RISCV_FS0_REGNUM,
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SIM_RISCV_FS1_REGNUM,
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SIM_RISCV_FA0_REGNUM,
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SIM_RISCV_FA1_REGNUM,
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SIM_RISCV_FA2_REGNUM,
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SIM_RISCV_FA3_REGNUM,
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SIM_RISCV_FA4_REGNUM,
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SIM_RISCV_FA5_REGNUM,
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SIM_RISCV_FA6_REGNUM,
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SIM_RISCV_FA7_REGNUM,
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SIM_RISCV_FS2_REGNUM,
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SIM_RISCV_FS3_REGNUM,
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SIM_RISCV_FS4_REGNUM,
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SIM_RISCV_FS5_REGNUM,
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SIM_RISCV_FS6_REGNUM,
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SIM_RISCV_FS7_REGNUM,
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SIM_RISCV_FS8_REGNUM,
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SIM_RISCV_FS9_REGNUM,
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SIM_RISCV_FS10_REGNUM,
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SIM_RISCV_FS11_REGNUM,
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SIM_RISCV_FT8_REGNUM,
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SIM_RISCV_FT9_REGNUM,
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SIM_RISCV_FT10_REGNUM,
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SIM_RISCV_FT11_REGNUM,
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#define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM
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#define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1
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#define DECLARE_CSR(name, num, ...) SIM_RISCV_ ## num ## _REGNUM,
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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#define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1
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SIM_RISCV_LAST_REGNUM
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};
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