mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-06 12:09:26 +08:00
080a488354
This fixes a problem originally reported at
https://github.com/riscv/riscv-binutils-gdb/issues/173
If you have code linked at address zero, you can have a lui instruction
loading a value 0x800 which gets relaxed to a c.lui which is valid (c.lui 0x1
followed by addi -0x800). Relaxation can reduce the value below 0x800 at which
point the c.lui 0x0 is no longer valid. We can fix this by converting the
c.lui to a c.li which can load 0.
bfd/
* elfnn-riscv.c (perform_relocation) <R_RISCV_RVC_LUI>: If
RISCV_CONST_HIGH_PART (value) is zero, then convert c.lui instruction
to c.li instruction, and use ENCODE_RVC_IMM to set value.
ld/
* testsuite/ld-riscv-elf/c-lui-2.d: New.
* testsuite/ld-riscv-elf/c-lui-2.ld: New.
* testsuite/ld-riscv-elf/c-lui-2.s: New.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run the c-lui-2 test.
20 lines
339 B
Makefile
20 lines
339 B
Makefile
#name: c.lui to c.li relaxation
|
|
#source: c-lui-2.s
|
|
#as: -march=rv32ic
|
|
#ld: -melf32lriscv -Tc-lui-2.ld
|
|
#objdump: -d -M no-aliases,numeric
|
|
|
|
.*: file format .*
|
|
|
|
|
|
Disassembly of section \.text:
|
|
|
|
.* <_start>:
|
|
.*: 4501 c.li x10,0
|
|
.*: 7fe00513 addi x10,x0,2046
|
|
...
|
|
|
|
.* <foo>:
|
|
.*: 8082 c.jr x1
|
|
#pass
|