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1d506c26d9
This commit is the result of the following actions: - Running gdb/copyright.py to update all of the copyright headers to include 2024, - Manually updating a few files the copyright.py script told me to update, these files had copyright headers embedded within the file, - Regenerating gdbsupport/Makefile.in to refresh it's copyright date, - Using grep to find other files that still mentioned 2023. If these files were updated last year from 2022 to 2023 then I've updated them this year to 2024. I'm sure I've probably missed some dates. Feel free to fix them up as you spot them.
214 lines
5.5 KiB
C
214 lines
5.5 KiB
C
/* Main simulator entry points specific to the FRV.
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Copyright (C) 1998-2024 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include <stdlib.h>
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#include "sim/callback.h"
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#define WANT_CPU
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "sim-options.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "bfd/elf-bfd.h"
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static void free_state (SIM_DESC);
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/* Cover function of sim_state_free to free the cpu buffers as well. */
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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extern const SIM_MACH * const frv_sim_machs[];
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/* Create an instance of the simulator. */
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *callback, bfd *abfd,
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char * const *argv)
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{
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char c;
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int i;
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unsigned long elf_flags = 0;
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SIM_DESC sd = sim_state_alloc (kind, callback);
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/* Set default options before parsing user options. */
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STATE_MACHS (sd) = frv_sim_machs;
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STATE_MODEL_NAME (sd) = "fr500";
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current_alignment = STRICT_ALIGNMENT;
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current_target_byte_order = BFD_ENDIAN_BIG;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all_extra (sd, 0, sizeof (struct frv_sim_cpu)) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* These options override any module options.
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Obviously ambiguity should be avoided, however the caller may wish to
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augment the meaning of an option. */
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sim_add_option_table (sd, NULL, frv_options);
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/* The parser will print an error message for us, so we silently return. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Allocate core managed memory if none specified by user.
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Use address 4 here in case the user wanted address 0 unmapped. */
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if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
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sim_do_commandf (sd, "memory region 0,0x%x", FRV_DEFAULT_MEM_SIZE);
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/* check for/establish the reference program image */
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if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* set machine and architecture correctly instead of defaulting to frv */
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{
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bfd *prog_bfd = STATE_PROG_BFD (sd);
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if (prog_bfd != NULL)
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{
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const struct elf_backend_data *backend_data;
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if (bfd_get_arch (prog_bfd) != bfd_arch_frv)
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{
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sim_io_eprintf (sd, "%s: \"%s\" is not a FRV object file\n",
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STATE_MY_NAME (sd),
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bfd_get_filename (prog_bfd));
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free_state (sd);
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return 0;
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}
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backend_data = get_elf_backend_data (prog_bfd);
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if (backend_data != NULL)
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backend_data->elf_backend_object_p (prog_bfd);
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elf_flags = elf_elfheader (prog_bfd)->e_flags;
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}
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Open a copy of the cpu descriptor table. */
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{
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CGEN_CPU_DESC cd = frv_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
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CGEN_ENDIAN_BIG);
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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CPU_CPU_DESC (cpu) = cd;
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CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
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CPU_ELF_FLAGS (cpu) = elf_flags;
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}
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frv_cgen_init_dis (cd);
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}
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU* cpu = STATE_CPU (sd, i);
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frv_initialize (cpu, sd);
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}
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return sd;
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}
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void
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frv_sim_close (SIM_DESC sd, int quitting)
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{
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int i;
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/* Terminate cache support. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU* cpu = STATE_CPU (sd, i);
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frv_cache_term (CPU_INSN_CACHE (cpu));
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frv_cache_term (CPU_DATA_CACHE (cpu));
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}
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, bfd *abfd, char * const *argv,
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char * const *env)
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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host_callback *cb = STATE_CALLBACK (sd);
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bfd_vma addr;
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if (abfd != NULL)
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addr = bfd_get_start_address (abfd);
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else
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addr = 0;
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sim_pc_set (current_cpu, addr);
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/* Standalone mode (i.e. `run`) will take care of the argv for us in
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sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
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with `gdb`), we need to handle it because the user can change the
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argv on the fly via gdb's 'run'. */
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if (STATE_PROG_ARGV (sd) != argv)
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{
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freeargv (STATE_PROG_ARGV (sd));
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STATE_PROG_ARGV (sd) = dupargv (argv);
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}
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if (STATE_PROG_ENVP (sd) != env)
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{
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freeargv (STATE_PROG_ENVP (sd));
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STATE_PROG_ENVP (sd) = dupargv (env);
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}
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cb->argv = STATE_PROG_ARGV (sd);
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cb->envp = STATE_PROG_ENVP (sd);
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return SIM_RC_OK;
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}
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