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Similar to ARM/AARCH64, we add mapping symbols in the symbol table, to mark the start addresses of data and instructions. The $d means data, and the $x means instruction. Then the disassembler uses these symbols to decide whether we should dump data or instruction. Consider the mapping-04 test case, $ cat tmp.s .text .option norelax .option norvc .fill 2, 4, 0x1001 .byte 1 .word 0 .balign 8 add a0, a0, a0 .fill 5, 2, 0x2002 add a1, a1, a1 .data .word 0x1 # No need to add mapping symbols. .word 0x2 $ riscv64-unknown-elf-as tmp.s -o tmp.o $ riscv64-unknown-elf-objdump -d tmp.o Disassembly of section .text: 0000000000000000 <.text>: 0: 00001001 .word 0x00001001 # Marked $d, .fill directive. 4: 00001001 .word 0x00001001 8: 00000001 .word 0x00000001 # .byte + part of .word. c: 00 .byte 0x00 # remaining .word. d: 00 .byte 0x00 # Marked $d, odd byte of alignment. e: 0001 nop # Marked $x, nops for alignment. 10: 00a50533 add a0,a0,a0 14: 20022002 .word 0x20022002 # Marked $d, .fill directive. 18: 20022002 .word 0x20022002 1c: 2002 .short 0x2002 1e: 00b585b3 add a1,a1,a1 # Marked $x. 22: 0001 nop # Section tail alignment. 24: 00000013 nop * Use $d and $x to mark the distribution of data and instructions. Alignments of code are recognized as instructions, since we usually fill nops for them. * If the alignment have odd bytes, then we cannot just fill the nops into the spaces. We always fill an odd byte 0x00 at the start of the spaces. Therefore, add a $d mapping symbol for the odd byte, to tell disassembler that it isn't an instruction. The behavior is same as Arm and Aarch64. The elf/linux toolchain regressions all passed. Besides, I also disable the mapping symbols internally, but use the new objudmp, the regressions passed, too. Therefore, the new objudmp should dump the objects corretly, even if they don't have any mapping symbols. bfd/ pr 27916 * cpu-riscv.c (riscv_elf_is_mapping_symbols): Define mapping symbols. * cpu-riscv.h: extern riscv_elf_is_mapping_symbols. * elfnn-riscv.c (riscv_maybe_function_sym): Do not choose mapping symbols as a function name. (riscv_elf_is_target_special_symbol): Add mapping symbols. binutils/ pr 27916 * testsuite/binutils-all/readelf.s: Updated. * testsuite/binutils-all/readelf.s-64: Likewise. * testsuite/binutils-all/readelf.s-64-unused: Likewise. * testsuite/binutils-all/readelf.ss: Likewise. * testsuite/binutils-all/readelf.ss-64: Likewise. * testsuite/binutils-all/readelf.ss-64-unused: Likewise. gas/ pr 27916 * config/tc-riscv.c (make_mapping_symbol): Create a new mapping symbol. (riscv_mapping_state): Decide whether to create mapping symbol for frag_now. Only add the mapping symbols to text sections. (riscv_add_odd_padding_symbol): Add the mapping symbols for the riscv_handle_align, which have odd bytes spaces. (riscv_check_mapping_symbols): Remove any excess mapping symbols. (md_assemble): Marked as MAP_INSN. (riscv_frag_align_code): Marked as MAP_INSN. (riscv_init_frag): Add mapping symbols for frag, it usually called by frag_var. Marked as MAP_DATA for rs_align and rs_fill, and marked as MAP_INSN for rs_align_code. (s_riscv_insn): Marked as MAP_INSN. (riscv_adjust_symtab): Call riscv_check_mapping_symbols. * config/tc-riscv.h (md_cons_align): Defined to riscv_mapping_state with MAP_DATA. (TC_SEGMENT_INFO_TYPE): Record mapping state for each segment. (TC_FRAG_TYPE): Record the first and last mapping symbols for the fragments. The first mapping symbol must be placed at the start of the fragment. (TC_FRAG_INIT): Defined to riscv_init_frag. * testsuite/gas/riscv/mapping-01.s: New testcase. * testsuite/gas/riscv/mapping-01a.d: Likewise. * testsuite/gas/riscv/mapping-01b.d: Likewise. * testsuite/gas/riscv/mapping-02.s: Likewise. * testsuite/gas/riscv/mapping-02a.d: Likewise. * testsuite/gas/riscv/mapping-02b.d: Likewise. * testsuite/gas/riscv/mapping-03.s: Likewise. * testsuite/gas/riscv/mapping-03a.d: Likewise. * testsuite/gas/riscv/mapping-03b.d: Likewise. * testsuite/gas/riscv/mapping-04.s: Likewise. * testsuite/gas/riscv/mapping-04a.d: Likewise. * testsuite/gas/riscv/mapping-04b.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04a.d: Likewise. * testsuite/gas/riscv/mapping-norelax-04b.d: Likewise. * testsuite/gas/riscv/no-relax-align.d: Updated. * testsuite/gas/riscv/no-relax-align-2.d: Likewise. include/ pr 27916 * opcode/riscv.h (enum riscv_seg_mstate): Added. opcodes/ pr 27916 * riscv-dis.c (last_map_symbol, last_stop_offset, last_map_state): Added to dump sections with mapping symbols. (riscv_get_map_state): Get the mapping state from the symbol. (riscv_search_mapping_symbol): Check the sorted symbol table, and then find the suitable mapping symbol. (riscv_data_length): Decide which data size we should print. (riscv_disassemble_data): Dump the data contents. (print_insn_riscv): Handle the mapping symbols. (riscv_symbol_is_valid): Marked mapping symbols as invalid.
152 lines
4.5 KiB
C
152 lines
4.5 KiB
C
/* BFD backend for RISC-V
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Copyright (C) 2011-2021 Free Software Foundation, Inc.
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Contributed by Andrew Waterman (andrew@sifive.com).
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Based on MIPS target.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#include "sysdep.h"
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#include "bfd.h"
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#include "libbfd.h"
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#include "cpu-riscv.h"
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static const bfd_arch_info_type *
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riscv_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
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{
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if (a->arch != b->arch)
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return NULL;
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/* Machine compatibility is checked in
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_bfd_riscv_elf_merge_private_bfd_data. */
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return a;
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}
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/* Return TRUE if STRING matches the architecture described by INFO. */
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static bool
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riscv_scan (const struct bfd_arch_info *info, const char *string)
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{
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if (bfd_default_scan (info, string))
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return true;
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/* The incoming STRING might take the form of riscv:rvXXzzz, where XX is
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32 or 64, and zzz are one or more extension characters. As we
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currently only have 3 architectures defined, 'riscv', 'riscv:rv32',
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and 'riscv:rv64', we would like to ignore the zzz for the purpose of
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matching here.
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However, we don't want the default 'riscv' to match over a more
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specific 'riscv:rv32' or 'riscv:rv64', so in the case of the default
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architecture (with the shorter 'riscv' name) we don't allow any
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special matching, but for the 'riscv:rvXX' cases, we allow a match
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with any additional trailing characters being ignored. */
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if (!info->the_default
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&& strncasecmp (string, info->printable_name,
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strlen (info->printable_name)) == 0)
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return true;
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return false;
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}
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#define N(BITS, NUMBER, PRINT, DEFAULT, NEXT) \
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{ \
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BITS, /* Bits in a word. */ \
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BITS, /* Bits in an address. */ \
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8, /* Bits in a byte. */ \
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bfd_arch_riscv, \
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NUMBER, \
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"riscv", \
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PRINT, \
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3, \
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DEFAULT, \
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riscv_compatible, \
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riscv_scan, \
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bfd_arch_default_fill, \
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NEXT, \
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0 /* Maximum offset of a reloc from the start of an insn. */\
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}
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/* This enum must be kept in the same order as arch_info_struct. */
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enum
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{
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I_riscv64,
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I_riscv32
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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/* This array must be kept in the same order as the anonymous enum above,
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and each entry except the last should end with NN (my enum value). */
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (64, bfd_mach_riscv64, "riscv:rv64", false, NN (I_riscv64)),
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N (32, bfd_mach_riscv32, "riscv:rv32", false, NULL)
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};
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/* The default architecture is riscv:rv64. */
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const bfd_arch_info_type bfd_riscv_arch =
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N (64, 0, "riscv", true, &arch_info_struct[0]);
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/* List for all supported ISA spec versions. */
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const struct riscv_spec riscv_isa_specs[] =
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{
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{"2.2", ISA_SPEC_CLASS_2P2},
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{"20190608", ISA_SPEC_CLASS_20190608},
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{"20191213", ISA_SPEC_CLASS_20191213},
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};
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/* List for all supported privileged spec versions. */
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const struct riscv_spec riscv_priv_specs[] =
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{
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{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
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{"1.10", PRIV_SPEC_CLASS_1P10},
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{"1.11", PRIV_SPEC_CLASS_1P11},
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};
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/* Get the corresponding CSR version class by giving privilege
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version numbers. It is usually used to convert the priv
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attribute numbers into the corresponding class. */
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void
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riscv_get_priv_spec_class_from_numbers (unsigned int major,
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unsigned int minor,
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unsigned int revision,
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enum riscv_spec_class *class)
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{
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enum riscv_spec_class class_t = *class;
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char buf[36];
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if (revision != 0)
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snprintf (buf, sizeof (buf), "%u.%u.%u", major, minor, revision);
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else
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snprintf (buf, sizeof (buf), "%u.%u", major, minor);
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RISCV_GET_PRIV_SPEC_CLASS (buf, class_t);
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*class = class_t;
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}
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/* Define mapping symbols for riscv. */
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bool
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riscv_elf_is_mapping_symbols (const char *name)
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{
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return (!strncmp (name, "$d", 2)
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|| !strncmp (name, "$x", 2));
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}
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