Nelson Chu c2137f55ad RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. ... https://github.com/riscv/riscv-asm-manual/pull/61 We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h and zext.w. In a certain sense, zext.b is not a pseudo - It is an alias of andi. Similarly, sext.b and sext.h are aliases of other rvb instructions, when we enable b extension; But they are pseudos when we just enable rvi. However, this patch does not consider the rvb cases. Besides, zext.w is only valid in rv64. gas/ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef to expand the zext and sext pseudos, to give them a chance to be expanded into c-ext instructions. (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. * testsuite/gas/riscv/ext.s: New testcase. * testsuite/gas/riscv/ext-32.d: Likewise. * testsuite/gas/riscv/ext-64.d: Likewise. include/ * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. opcodes/ * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].		2020-12-10 10:50:44 +08:00
..
po	opcodes/po/es.po: Remove the duplicated entry	2020-10-22 05:21:35 -07:00
.gitignore
aarch64-asm-2.c	aarch64: Limit Rt register number for LS64 load/store instructions	2020-11-09 11:19:44 +00:00
aarch64-asm.c	aarch64: Add DSB instruction Armv8.7-a variant	2020-10-28 14:05:05 +00:00
aarch64-asm.h	aarch64: Add DSB instruction Armv8.7-a variant	2020-10-28 14:05:05 +00:00
aarch64-dis-2.c	aarch64: Limit Rt register number for LS64 load/store instructions	2020-11-09 11:19:44 +00:00
aarch64-dis.c	aarch64: Add DSB instruction Armv8.7-a variant	2020-10-28 14:05:05 +00:00
aarch64-dis.h	aarch64: Add DSB instruction Armv8.7-a variant	2020-10-28 14:05:05 +00:00
aarch64-gen.c
aarch64-opc-2.c	aarch64: Limit Rt register number for LS64 load/store instructions	2020-11-09 11:19:44 +00:00
aarch64-opc.c	aarch64: Update LS64 feature with system register	2020-11-09 11:37:32 +00:00
aarch64-opc.h	aarch64: Add DSB instruction Armv8.7-a variant	2020-10-28 14:05:05 +00:00
aarch64-tbl.h	aarch64: Extract Condition flag manipulation feature from Armv8.4-A	2020-11-16 21:07:17 +00:00
aclocal.m4
alpha-dis.c
alpha-opc.c
arc-dis.c	arc: Detect usage of illegal double register pairs	2020-07-14 14:51:15 +03:00
arc-dis.h
arc-ext-tbl.h
arc-ext.c	Replace "if (x) free (x)" with "free (x)", opcodes	2020-05-21 10:45:33 +09:30
arc-ext.h
arc-fxi.h
arc-nps400-tbl.h
arc-opc.c	arc: Update vector instructions.	2020-07-07 16:01:48 +03:00
arc-regs.h
arc-tbl.h	arc: Update vector instructions.	2020-07-07 16:01:48 +03:00
arm-dis.c	C++ comments	2020-06-29 10:07:56 +09:30
avr-dis.c
bfin-dis.c	ubsan: bfin-dis.c:160 shift exponent 32 is too large	2020-09-02 16:30:44 +09:30
bpf-asm.c
bpf-desc.c	bpf: xBPF SDIV, SMOD instructions	2020-09-18 10:04:23 -07:00
bpf-desc.h	bpf: xBPF SDIV, SMOD instructions	2020-09-18 10:04:23 -07:00
bpf-dis.c	cpu,gas,opcodes: remove no longer needed workaround from the BPF port	2020-06-04 16:17:42 +02:00
bpf-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
bpf-opc.c	bpf: xBPF SDIV, SMOD instructions	2020-09-18 10:04:23 -07:00
bpf-opc.h	bpf: xBPF SDIV, SMOD instructions	2020-09-18 10:04:23 -07:00
cgen-asm.c	Fix spelling mistakes	2020-10-05 14:20:15 +01:00
cgen-asm.in
cgen-bitset.c
cgen-dis.c	Fix spelling mistakes	2020-10-05 14:20:15 +01:00
cgen-dis.in	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
cgen-ibld.in	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
cgen-opc.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
cgen.sh
ChangeLog	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	2020-12-10 10:50:44 +08:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-2017
ChangeLog-2018
ChangeLog-2019
ChangeLog-9297
ChangeLog-9899
config.in
configure	Update version to 2.35.50 and regenerate files	2020-07-04 10:34:23 +01:00
configure.ac
configure.com
cr16-dis.c	cr16 disassembly error of disp20 fields	2020-08-30 20:49:32 +09:30
cr16-opc.c	C++ comments	2020-06-29 10:07:56 +09:30
cris-dis.c
cris-opc.c
crx-dis.c	ubsan: crx-dis.c:571 left shift of negative value	2020-09-02 16:30:44 +09:30
crx-opc.c
csky-dis.c	CSKY: Fix and add some instructions for VDSPV1.	2020-10-26 16:13:55 +08:00
csky-opc.h	CSKY: Change plsl.u16 to plsl.16.	2020-10-26 16:26:32 +08:00
d10v-dis.c
d10v-opc.c
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c
dis-init.c
disassemble.c	RISC-V: Dump CSR according to the elf privileged spec attributes.	2020-12-10 10:43:18 +08:00
disassemble.h	RISC-V: Dump CSR according to the elf privileged spec attributes.	2020-12-10 10:43:18 +08:00
dlx-dis.c
epiphany-asm.c
epiphany-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
epiphany-desc.h
epiphany-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
epiphany-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
fr30-desc.h
fr30-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
fr30-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
frv-desc.h
frv-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
frv-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
frv-opc.c
frv-opc.h
ft32-dis.c	C++ comments	2020-06-29 10:07:56 +09:30
ft32-opc.c
h8300-dis.c
hppa-dis.c
i386-dis-evex-len.h	x86: simplify decode of opcodes valid with (embedded) 66 prefix only	2020-07-14 10:33:40 +02:00
i386-dis-evex-mod.h	x86: drop Rdq, Rd, and MaskR	2020-07-14 10:42:33 +02:00
i386-dis-evex-prefix.h	x86: drop Rdq, Rd, and MaskR	2020-07-14 10:42:33 +02:00
i386-dis-evex-reg.h	x86: simplify decode of opcodes valid with (embedded) 66 prefix only	2020-07-14 10:33:40 +02:00
i386-dis-evex-w.h	x86: drop Rdq, Rd, and MaskR	2020-07-14 10:42:33 +02:00
i386-dis-evex.h	x86: drop Rdq, Rd, and MaskR	2020-07-14 10:42:33 +02:00
i386-dis.c	x86: Do not dump DS/CS segment overrides for branch hints	2020-11-29 09:08:56 -08:00
i386-gen.c	Add AMD znver3 processor support	2020-10-20 13:58:04 -07:00
i386-init.h	Add AMD znver3 processor support	2020-10-20 13:58:04 -07:00
i386-opc.c
i386-opc.h	Add AMD znver3 processor support	2020-10-20 13:58:04 -07:00
i386-opc.tbl	Add AMD znver3 processor support	2020-10-20 13:58:04 -07:00
i386-reg.tbl	x86: Add support for Intel AMX instructions	2020-07-10 05:18:34 -07:00
i386-tbl.h	Add AMD znver3 processor support	2020-10-20 13:58:04 -07:00
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
ip2k-desc.h
ip2k-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
ip2k-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
iq2000-desc.h
iq2000-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
iq2000-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
lm32-desc.h
lm32-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
lm32-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
m32c-desc.h
m32c-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
m32c-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
m32r-desc.h
m32r-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
m32r-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c	Disallow PC relative for CMPI on MC68000/10	2020-04-21 16:53:36 +02:00
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am
Makefile.in
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c	Replace "if (x) free (x)" with "free (x)", opcodes	2020-05-21 10:45:33 +09:30
mep-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
mep-desc.h
mep-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
mep-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips16-opc.c
mips-dis.c
mips-formats.h
mips-opc.c
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c	C++ comments	2020-06-29 10:07:56 +09:30
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
mt-desc.h
mt-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
mt-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
mt-opc.c
mt-opc.h
nds32-asm.c
nds32-asm.h
nds32-dis.c
nds32-opc.h
nfp-dis.c
nios2-dis.c	ubsan: nios2: undefined shift	2020-05-28 22:08:42 +09:30
nios2-opc.c
ns32k-dis.c	asan: ns32k: use of uninitialized value	2020-05-28 21:11:32 +09:30
opc2c.c
opintl.h
or1k-asm.c	or1k: Regenerate opcodes after removing 32-bit support	2020-05-19 20:41:03 +09:00
or1k-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
or1k-desc.h	or1k: Regenerate opcodes after removing 32-bit support	2020-05-19 20:41:03 +09:00
or1k-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
or1k-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
or1k-opc.c	or1k: Regenerate opcodes after removing 32-bit support	2020-05-19 20:41:03 +09:00
or1k-opc.h	or1k: Regenerate opcodes after removing 32-bit support	2020-05-19 20:41:03 +09:00
or1k-opinst.c	or1k: Regenerate opcodes after removing 32-bit support	2020-05-19 20:41:03 +09:00
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c	Tidy elf_symbol_from	2020-09-16 16:41:33 +09:30
ppc-opc.c	Correct vcmpsq, vcmpuq and xvtlsbb BF field	2020-08-19 08:47:35 +09:30
pru-dis.c
pru-opc.c	Add support for the LMBD (left-most bit detect) instruction to the PRU assembler.	2020-11-09 12:41:09 +00:00
riscv-dis.c	RISC-V: Dump CSR according to the elf privileged spec attributes.	2020-12-10 10:43:18 +08:00
riscv-opc.c	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.	2020-12-10 10:50:44 +08:00
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c	rx-dis.c:103:3: suspicious concatenation of string literals	2020-09-21 18:20:58 +09:30
s12z-dis.c
s12z-opc.c	C++ comments	2020-06-29 10:07:56 +09:30
s12z-opc.h
s390-dis.c
s390-mkopc.c	PR26279 Work around maybe-uninitialized warning in s390-mkopc.c	2020-07-29 19:46:44 +02:00
s390-opc.c	IBM Z: Add risbgz and risbgnz extended mnemonics	2020-12-04 09:14:02 +01:00
s390-opc.txt	IBM Z: Add risbgz and risbgnz extended mnemonics	2020-12-04 09:14:02 +01:00
score7-dis.c
score-dis.c
score-opc.h
sh-dis.c	Fix the disassmbly of SH instructions which have an unsigned 8-bit immediate operand.	2020-04-29 13:13:55 +01:00
sh-opc.h	Also use unsigned 8-bit immediate values for the LDRC and SETRC insns.	2020-04-29 16:09:38 +01:00
sparc-dis.c	Replace "if (x) free (x)" with "free (x)", opcodes	2020-05-21 10:45:33 +09:30
sparc-opc.c
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c	Replace "if (x) free (x)" with "free (x)", opcodes	2020-05-21 10:45:33 +09:30
tic6x-dis.c
tic30-dis.c	Fix spelling mistakes	2020-10-05 14:20:15 +01:00
tic54x-dis.c	C++ comments	2020-06-29 10:07:56 +09:30
tic54x-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c	ubsan: v850-opc.c:412 left shift cannot be represented	2020-09-02 16:30:44 +09:30
vax-dis.c	PR26504, ASAN: parse_disassembler_options vax-dis.c:142	2020-08-25 23:07:10 +09:30
visium-dis.c
visium-opc.c
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
xc16x-desc.h
xc16x-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
xc16x-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
xc16x-opc.c
xc16x-opc.h
xgate-dis.c	C++ comments	2020-06-29 10:07:56 +09:30
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c	opcodes: support insn endianness in cgen_cpu_open	2020-06-04 16:17:42 +02:00
xstormy16-desc.h
xstormy16-dis.c	opcodes: discriminate endianness and insn-endianness in CGEN ports	2020-06-04 16:17:42 +02:00
xstormy16-ibld.c	ubsan: *-ibld.c	2020-09-02 16:30:44 +09:30
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c	Replace "if (x) free (x)" with "free (x)", opcodes	2020-05-21 10:45:33 +09:30
z8k-dis.c
z8k-opc.h	Z8k: fix sout/soudb opcodes with direct address	2020-08-04 22:31:42 +02:00
z8kgen.c	Z8k: fix sout/soudb opcodes with direct address	2020-08-04 22:31:42 +02:00
z80-dis.c