mirror of
https://sourceware.org/git/binutils-gdb.git
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9d7c4ba5e5
* addb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>.
* andb.s: Likewise.
* cmpb.s: Likewise.
* orb.s: Likewise.
* subb.s: Likewise.
* xorb.s: Likewise.
* movb.s: Add special case reg,<@reg+ / @reg- / @+reg / @-reg>
@reg+,@reg+ / @-reg,@-reg.
* movw.s: Likewise.
* movl.s: Likewise.
402 lines
8.4 KiB
ArmAsm
402 lines
8.4 KiB
ArmAsm
# Hitachi H8 testcase 'xor.b'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# xor.b #xx:8, rd ; d rd xxxxxxxx
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# xor.b #xx:8, @erd ; 7 d rd ???? d ???? xxxxxxxx
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# xor.b #xx:8, @erd+ ; 0 1 7 4 6 c rd 1??? d ???? xxxxxxxx
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# xor.b #xx:8, @erd- ; 0 1 7 6 6 c rd 1??? d ???? xxxxxxxx
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# xor.b #xx:8, @+erd ; 0 1 7 5 6 c rd 1??? d ???? xxxxxxxx
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# xor.b #xx:8, @-erd ; 0 1 7 7 6 c rd 1??? d ???? xxxxxxxx
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# xor.b rs, rd ; 1 5 rs rd
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# xor.b reg8, @erd ; 7 d rd ???? 1 5 rs ????
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# xor.b reg8, @erd+ ; 0 1 7 9 8 rd 5 rs
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# xor.b reg8, @erd- ; 0 1 7 9 a rd 5 rs
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# xor.b reg8, @+erd ; 0 1 7 9 9 rd 5 rs
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# xor.b reg8, @-erd ; 0 1 7 9 b rd 5 rs
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#
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# xorc #xx:8, ccr ;
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# xorc #xx:8, exr ;
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# Coming soon:
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# ...
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.data
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pre_byte: .byte 0
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byte_dest: .byte 0xa5
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post_byte: .byte 0
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start
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xor_b_imm8_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; xor.b #xx:8,Rd
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xor.b #0xff, r0l ; Immediate 8-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xa55a r0 ; xor result: a5 ^ ff
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a55a er0 ; xor result: a5 ^ ff
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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xor_b_imm8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b #xx:8,@eRd
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mov #byte_dest, er0
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xor.b #0xff:8, @er0 ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x7d00
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;;; .word 0xd0ff
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest, er0 ; er0 still contains address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the xor to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x5a, r0l
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beq .L1
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fail
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.L1:
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xor_b_imm8_postinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b #xx:8,@eRd+
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mov #byte_dest, er0
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xor.b #0xff:8, @er0+ ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0xd0ff
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 post_byte, er0 ; er0 contains address plus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the xor to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa5, r0l
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beq .L2
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fail
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.L2:
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xor_b_imm8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b #xx:8,@eRd-
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mov #byte_dest, er0
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xor.b #0xff:8, @er0- ; Immediate 8-bit src, reg indirect dst
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0xd0ff
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 pre_byte, er0 ; er0 contains address minus one
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the xor to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x5a, r0l
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beq .L3
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fail
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.L3:
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.endif
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xor_b_reg8_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; xor.b Rs,Rd
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mov.b #0xff, r0h
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xor.b r0h, r0l ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr16 0xff5a r0 ; xor result: a5 ^ ff
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5ff5a er0 ; xor result: a5 ^ ff
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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xor_b_reg8_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b rs8,@eRd ; xor reg8 to register indirect
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mov #byte_dest, er0
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mov #0xff, r1l
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xor.b r1l, @er0 ; reg8 src, reg indirect dest
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;;; .word 0x7d00
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;;; .word 0x1590
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest er0 ; er0 still contains address
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test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa5, r0l
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beq .L4
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fail
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.L4:
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xor_b_reg8_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b rs8,@eRd+ ; xor reg8 to register post-increment
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mov #byte_dest, er0
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mov #0xff, r1l
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xor.b r1l, @er0+ ; reg8 src, reg post-increment dest
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;;; .word 0x0179
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;;; .word 0x8059
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test_carry_clear ; H=0 N=0 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 post_byte er0 ; er0 contains address plus one
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test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0x5a, r0l
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beq .L5
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fail
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.L5:
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;; special case same register
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mov.l #byte_dest, er0
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mov.b r0l, r1l
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mov.b @er0, r1h
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xor.b r0l, @er0+
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inc.b r1l
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xor.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L25
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fail
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.L25:
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mov.b r1h, @byte_dest
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xor_b_reg8_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xor.b rs8,@eRd- ; xor reg8 to register post-decrement
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mov #byte_dest, er0
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mov #0xff, r1l
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xor.b r1l, @er0- ; reg8 src, reg indirect dest
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;;; .word 0x0179
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;;; .word 0xa059
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test_carry_clear ; H=0 N=1 Z=0 V=0 C=0
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 pre_byte er0 ; er0 contains address minus one
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test_h_gr32 0xa5a5a5ff er1 ; er1 has the test load
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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;; Now check the result of the or to memory.
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sub.b r0l, r0l
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mov.b @byte_dest, r0l
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cmp.b #0xa5, r0l
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beq .L6
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fail
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.L6:
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;; special case same register
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mov.l #byte_dest, er0
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mov.b r0l, r1l
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mov.b @er0, r1h
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xor.b r0l, @er0-
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dec.b r1l
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xor.b r1h, r1l
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mov.b @byte_dest, r0l
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cmp.b r1l, r0l
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beq .L26
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fail
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.L26:
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.endif ; h8sx
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xorc_imm8_ccr:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; xorc #xx:8,ccr
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test_neg_clear
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xorc #0x8, ccr ; Immediate 8-bit operand (neg flag)
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test_neg_set
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xorc #0x8, ccr
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test_neg_clear
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test_zero_clear
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xorc #0x4, ccr ; Immediate 8-bit operand (zero flag)
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test_zero_set
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xorc #0x4, ccr
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test_zero_clear
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test_ovf_clear
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xorc #0x2, ccr ; Immediate 8-bit operand (overflow flag)
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test_ovf_set
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xorc #0x2, ccr
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test_ovf_clear
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test_carry_clear
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xorc #0x1, ccr ; Immediate 8-bit operand (carry flag)
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test_carry_set
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xorc #0x1, ccr
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test_carry_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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xorc_imm8_exr:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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ldc #0, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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set_ccr_zero
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;; xorc #xx:8,exr
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xorc #0x80, exr
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test_cc_clear
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stc exr, r0l
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test_h_gr8 0x80, r0l
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xorc #0x80, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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xorc #0x4, exr
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stc exr, r0l
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test_h_gr8 4, r0l
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xorc #0x4, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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xorc #0x2, exr ; Immediate 8-bit operand (overflow flag)
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stc exr, r0l
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test_h_gr8 2, r0l
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xorc #0x2, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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xorc #0x1, exr ; Immediate 8-bit operand (carry flag)
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stc exr, r0l
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test_h_gr8 1, r0l
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xorc #0x1, exr
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stc exr, r0l
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test_h_gr8 0, r0l
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test_h_gr32 0xa5a5a500 er0
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif ; not h8300 or h8300h
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pass
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exit 0
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