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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
376 lines
7.7 KiB
ArmAsm
376 lines
7.7 KiB
ArmAsm
# Hitachi H8 testcase 'ldc'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.data
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byte_pre:
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.byte 0
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byte_src:
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.byte 0xff
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byte_post:
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.byte 0
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start
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ldc_imm8_ccr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0xff, ccr ; set all ccr flags high, immediate operand
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bcs .L1 ; carry flag set?
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fail
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.L1: bvs .L2 ; overflow flag set?
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fail
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.L2: beq .L3 ; zero flag set?
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fail
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.L3: bmi .L4 ; neg flag set?
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fail
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.L4:
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ldc #0, ccr ; set all ccr flags low, immediate operand
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bcc .L5 ; carry flag clear?
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fail
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.L5: bvc .L6 ; overflow flag clear?
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fail
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.L6: bne .L7 ; zero flag clear?
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fail
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.L7: bpl .L8 ; neg flag clear?
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fail
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.L8:
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test_cc_clear
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test_grs_a5a5
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ldc_reg8_ccr:
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set_grs_a5a5
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set_ccr_zero
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mov #0xff, r0h
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ldc r0h, ccr ; set all ccr flags high, reg operand
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bcs .L11 ; carry flag set?
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fail
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.L11: bvs .L12 ; overflow flag set?
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fail
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.L12: beq .L13 ; zero flag set?
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fail
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.L13: bmi .L14 ; neg flag set?
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fail
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.L14:
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mov #0, r0h
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ldc r0h, ccr ; set all ccr flags low, reg operand
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bcc .L15 ; carry flag clear?
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fail
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.L15: bvc .L16 ; overflow flag clear?
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fail
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.L16: bne .L17 ; zero flag clear?
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fail
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.L17: bpl .L18 ; neg flag clear?
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fail
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.L18:
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test_cc_clear
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test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
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ldc_imm8_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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ldc #0x87, exr ; set exr to 0x87
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stc exr, r0l ; retrieve and check exr value
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cmp.b #0x87, r0l
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beq .L19
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fail
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.L19:
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test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_reg8_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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mov #0x87, r0h
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ldc r0h, exr ; set exr to 0x87
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stc exr, r0l ; retrieve and check exr value
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cmp.b #0x87, r0l
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beq .L21
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fail
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.L21:
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test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_abs16_ccr:
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set_grs_a5a5
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set_ccr_zero
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ldc @byte_src:16, ccr ; abs16 src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_abs16_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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ldc @byte_src:16, exr ; abs16 src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_abs32_ccr:
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set_grs_a5a5
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set_ccr_zero
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ldc @byte_src:32, ccr ; abs32 src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_abs32_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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ldc @byte_src:32, exr ; abs32 src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_disp16_ccr:
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set_grs_a5a5
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set_ccr_zero
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mov #byte_pre, er1
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ldc @(1:16, er1), ccr ; disp16 src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_h_gr32 byte_pre, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_disp16_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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mov #byte_post, er1
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ldc @(-1:16, er1), exr ; disp16 src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_h_gr32 byte_post, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_disp32_ccr:
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set_grs_a5a5
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set_ccr_zero
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mov #byte_pre, er1
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ldc @(1:32, er1), ccr ; disp32 src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_h_gr32 byte_pre, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_disp32_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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mov #byte_post, er1
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ldc @(-1:32, er1), exr ; disp16 src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_h_gr32 byte_post, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_postinc_ccr:
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set_grs_a5a5
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set_ccr_zero
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mov #byte_src, er1
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ldc @er1+, ccr ; postinc src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_h_gr32 byte_src+2, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_postinc_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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mov #byte_src, er1
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ldc @er1+, exr ; postinc src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_h_gr32 byte_src+2, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_ind_ccr:
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set_grs_a5a5
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set_ccr_zero
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mov #byte_src, er1
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ldc @er1, ccr ; postinc src
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stc ccr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
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test_h_gr32 byte_src, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_ind_exr:
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set_grs_a5a5
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set_ccr_zero
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ldc #0, exr
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mov #byte_src, er1
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ldc @er1, exr ; postinc src
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stc exr, r0l ; copy into general reg
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test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
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test_h_gr32 byte_src, er1 ; er1 still contains address
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
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ldc_reg_sbr:
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set_grs_a5a5
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set_ccr_zero
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mov #0xaaaaaaaa, er0
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ldc er0, sbr ; set sbr to 0xaaaaaaaa
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stc sbr, er1 ; retreive and check sbr value
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test_h_gr32 0xaaaaaaaa er1
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test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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ldc_reg_vbr:
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set_grs_a5a5
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set_ccr_zero
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mov #0xaaaaaaaa, er0
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ldc er0, vbr ; set sbr to 0xaaaaaaaa
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stc vbr, er1 ; retreive and check sbr value
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test_h_gr32 0xaaaaaaaa er1
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test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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pass
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exit 0
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