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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
51 lines
1.2 KiB
Plaintext
51 lines
1.2 KiB
Plaintext
# frv testcase for mp_exception
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# mach: frv fr500 fr400
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.include "testutils.inc"
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start
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.global mp_exception
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mpx:
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr7
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inc_gr_immed 0x0e0,gr7 ; address of exception handler
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set_bctrlr_0_0 gr7
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set_spr_immed 128,lcr
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set_spr_addr ok1,lr
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set_psr_et 1
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set_gr_immed 0,gr5
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set_spr_immed 0,msr0
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x7ffe,0x7ffe,fr11
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set_fr_iimmed 0xffff,0xffff,fr12
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set_fr_iimmed 0x0002,0x0001,fr13
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mqaddhss fr10,fr12,fr14
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test_fr_limmed 0x1233,0x5677,fr14
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test_fr_limmed 0x7fff,0x7fff,fr15
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test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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mtrap ; generate interrupt
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test_gr_immed 1,gr5
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and_spr_immed 0xffffc000,msr0 ; Clear msr0 fields
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mcmpsh fr10,fr11,fcc0 ; no exception
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test_spr_bits 0x7000,12,0,msr0; msr0.mtt is clear
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mtrap ; nop
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test_gr_immed 1,gr5
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pass
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; exception handler
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ok1:
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test_spr_bits 0x3c,2,0x2,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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inc_gr_immed 1,gr5
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rett 0
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fail
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