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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
90 lines
2.8 KiB
Plaintext
90 lines
2.8 KiB
Plaintext
# frv testcase for maddhus $FRi,$FRj,$FRj
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# mach: frv fr500 fr400
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.include "testutils.inc"
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start
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.global maddhus
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maddhus:
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set_fr_iimmed 0x0000,0x0000,fr10
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set_fr_iimmed 0x0000,0x0000,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0x0000,0x0000,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0xdead,0x0000,fr10
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set_fr_iimmed 0x0000,0xbeef,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0xdead,0xbeef,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0x0000,0xdead,fr10
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set_fr_iimmed 0xbeef,0x0000,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0xbeef,0xdead,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0x1234,0x5678,fr10
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set_fr_iimmed 0x1111,0x1111,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0x2345,0x6789,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf not set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0x7ffe,0x7ffe,fr10
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set_fr_iimmed 0x0002,0x0001,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0x8000,0x7fff,fr12
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 1,0,0,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set
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set_fr_iimmed 0xfffe,0xfffe,fr10
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set_fr_iimmed 0x0001,0x0002,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0xffff,0xffff,fr12
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test_spr_bits 0x3c,2,4,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_fr_iimmed 0x0002,0x0001,fr10
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set_fr_iimmed 0xfffe,0xfffe,fr11
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maddhus fr10,fr11,fr12
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test_fr_limmed 0xffff,0xffff,fr12
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test_spr_bits 0x3c,2,8,msr0 ; msr0.sie is set
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test_spr_bits 2,1,1,msr0 ; msr0.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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set_spr_immed 0,msr0
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set_spr_immed 0,msr1
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set_fr_iimmed 0x0001,0x0001,fr10
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set_fr_iimmed 0x8000,0x8000,fr11
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maddhus.p fr10,fr10,fr12
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maddhus fr11,fr11,fr13
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test_fr_limmed 0x0002,0x0002,fr12
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test_fr_limmed 0xffff,0xffff,fr13
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test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear
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test_spr_bits 2,1,0,msr0 ; msr0.ovf not set
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test_spr_bits 0x3c,2,0xc,msr1 ; msr1.sie is set
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test_spr_bits 2,1,1,msr1 ; msr1.ovf set
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test_spr_bits 1,0,1,msr0 ; msr0.aovf set
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test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt set
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pass
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