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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
135 lines
3.0 KiB
ArmAsm
135 lines
3.0 KiB
ArmAsm
// Test rl3 = ashift (rh0 by 7);
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// Test rl3 = lshift (rh0 by 7);
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# mach: bfin
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.include "testutils.inc"
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start
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init_r_regs 0;
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R0 = 0;
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ASTAT = R0;
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R0.L = 0x1;
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R0.H = 0x1;
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R7.L = R0.L << 4;
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DBGA ( R7.L , 0x0010 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R0.L = 0x8000;
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R0.H = 0x1;
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R7.L = R0.L >>> 4;
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DBGA ( R7.L , 0xf800 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R0.L = 0x0;
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R0.H = 0x1;
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R7.L = R0.L << 0;
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R7 = 0;
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R0.L = 0x1;
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R0.H = 0x8000;
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R7.H = R0.H >>> 4;
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0xf800 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R7 = 0;
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R0.L = 0x1;
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R0.H = 0x8000;
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R7.L = R0.H >>> 4;
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DBGA ( R7.L , 0xf800 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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// logic shifts
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R0 = 0;
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ASTAT = R0;
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R7 = 0;
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R0.L = 0x1;
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R0.H = 0x8000;
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R7.L = R0.H >> 4;
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DBGA ( R7.L , 0x0800 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R7 = 0;
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R0.L = 0x1;
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R0.H = 0x1;
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R7.H = R0.L << 4;
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0x0010 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R7 = 1;
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R0.L = 0x0;
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R0.H = 0x0;
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R7.L = R0.L << 0;
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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R0 = 0;
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ASTAT = R0;
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R7 = 1;
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R0.L = 0x1;
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R0.H = 0x0;
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R7.L = R0.L << 15;
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DBGA ( R7.L , 0x8000 );
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DBGA ( R7.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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pass
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