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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
338 lines
10 KiB
ArmAsm
338 lines
10 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_illaddr/lmu_excpt_illaddr.dsp
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// Description: LMU illegal address exceptions
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// Illegal core MMR: addr[19:16] != 0
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// Illegal core MMR: Illegal peripheral
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// Illegal core MMR: Illegal addr in peripheral
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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#ifndef SR_BASE
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#define SR_BASE 0xFF800000 // must match value used for sram_baddr inputs
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#endif
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#ifndef A_SRAM_BASE
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#define A_SRAM_BASE SR_BASE
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#endif
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#ifndef B_SRAM_BASE
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#define B_SRAM_BASE SR_BASE + 0x100000
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#endif
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#ifndef I_SRAM_BASE
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#define I_SRAM_BASE SR_BASE + 0x200000
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#endif
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#ifndef SCRATCH_SRAM_BASE
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#define SCRATCH_SRAM_BASE SR_BASE + 0x300000
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#endif
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#ifndef A_SRAM_SIZE
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#define A_SRAM_SIZE 0x4000
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#endif
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#ifndef B_SRAM_SIZE
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#define B_SRAM_SIZE 0x4000
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#endif
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#ifndef I_SRAM_SIZE
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#define I_SRAM_SIZE 0x4000
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#endif
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#ifndef SCRATCH_SRAM_SIZE
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#define SCRATCH_SRAM_SIZE 0x1000
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#endif
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CHECK_INIT(p5, 0xE0000000);
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// setup interrupt controller with exception handler address
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WR_MMR_LABEL(EVT3, handler, p0, r1);
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WR_MMR_LABEL(EVT15, int15, p0, r1);
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WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0);
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WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0);
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// Set up CPLB
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WR_MMR(DCPLB_ADDR1, SR_BASE, p0, r0); // SRAM segment: Non-cacheable
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WR_MMR(DCPLB_DATA1, ( CPLB_VALID | CPLB_L1SRAM | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
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WR_MMR(DCPLB_ADDR2, 0xE0000000, p0, r0); // CHECKREG segment: Non-cacheable
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WR_MMR(DCPLB_DATA2, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
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WR_MMR(DCPLB_ADDR15, 0xFFC00000, p0, r0); // MMRs: Non-cacheable
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WR_MMR(DCPLB_DATA15, ( CPLB_VALID | CPLB_DIRTY | CPLB_SUPV_WR | PAGE_SIZE_4M), p0, r0);
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WR_MMR(DMEM_CONTROL, (DMC_AB_SRAM | ENDCPLB | ENDM), p0, r0);
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CSYNC;
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// Write fault addr MMR to known state
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WR_MMR(DCPLB_FAULT_ADDR, 0, p0, r6);
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NOP;NOP;NOP;NOP;NOP; // in lieu of CSYNC
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// go to user mode. and enable exceptions
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LD32_LABEL(r0, User);
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RETI = R0;
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// But first raise interrupt 15 so we will run in supervisor mode.
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RAISE 15;
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NOP;
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RTI;
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// Nops to work around ICache bug
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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int15:
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NOP;NOP;NOP;NOP;NOP;
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//-------------------------------------------------------
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// First do stores
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//-------------------------------------------------------
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//
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// illegal core MMR: addr[19] !=0
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LD32(p1, 0xFFE80000);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X01: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE80000); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X01, r0); // RETX should be value of X01 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: addr[18] !=0
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LD32(p1, 0xFFE40000);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X02: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE40000); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X02, r0); // RETX should be value of X02 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: addr[17] !=0
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LD32(p1, 0xFFE20000);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X03: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE20000); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X03, r0); // RETX should be value of X03 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: addr[16] !=0
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LD32(p1, 0xFFE10000);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X04: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE10000); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X04, r0); // RETX should be value of X04 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal periperal (addr[15:12] > 8)
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LD32(p1, 0xFFE09000);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X10: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE09000); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X10, r0); // RETX should be value of X10 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 00
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LD32(p1, 0xFFE00408);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X20: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE00408); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X20, r0); // RETX should be value of X20 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 01
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LD32(p1, 0xFFE01408);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X21: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE01408); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X21, r0); // RETX should be value of X21 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 02
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LD32(p1, 0xFFE02114);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X22: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE02114); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X22, r0); // RETX should be value of X22 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 03
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LD32(p1, 0xFFE03010);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X23: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE03010); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X23, r0); // RETX should be value of X23 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 04
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LD32(p1, 0xFFE04008);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X24: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE04008); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X24, r0); // RETX should be value of X24 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 05
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LD32(p1, 0xFFE05010);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X25: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE05010); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X25, r0); // RETX should be value of X25 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 06
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LD32(p1, 0xFFE06104);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X26: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE06104); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X26, r0); // RETX should be value of X26 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 07
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LD32(p1, 0xFFE07204);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X27: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE07204); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X27, r0); // RETX should be value of X27 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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// illegal core MMR: illegal addr in peripheral 08
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LD32(p1, 0xFFE08108);
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LD32(p2, SRAM_BASE_ADDRESS); // Valid addr (handler will use move this to p1)
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LD32(r1, 0xDEADBEEF);
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R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first
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X28: [ P1 ] = R1; // Exception should occur here
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CHECKREG(r5,0x2e); // supv and EXCPT_PROT
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CHECKREG(r6, 0xFFE08108); // FAULT_ADDR should contain test address
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CHECKREG_SYM(r7, X28, r0); // RETX should be value of X28 (HARDCODED ADDR!!)
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//-------------------------------------------------------
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User:
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dbg_pass;
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//-------------------------------------------------------
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handler:
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R5 = SEQSTAT; // Get exception cause
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// read and check fail addr (addr_which_causes_exception)
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// should not be set for alignment exception
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RD_MMR(DCPLB_FAULT_ADDR, p0, r6);
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R7 = RETX; // get address of excepting instruction
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// align the offending address
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P1 = P2;
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RTX;
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// Nops to work around ICache bug
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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