mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-21 04:42:53 +08:00
1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
324 lines
6.2 KiB
ArmAsm
324 lines
6.2 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
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// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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//
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// Include Files
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//
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include(std.inc)
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include(selfcheck.inc)
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// Defines
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#ifndef TCNTL
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#define TCNTL 0xFFE03000
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#endif
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#ifndef TPERIOD
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#define TPERIOD 0xFFE03004
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#endif
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#ifndef TSCALE
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#define TSCALE 0xFFE03008
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#endif
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#ifndef TCOUNT
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#define TCOUNT 0xFFE0300c
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#endif
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#ifndef EVT
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#define EVT 0xFFE02000
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#endif
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#ifndef EVT15
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#define EVT15 0xFFE0203c
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#endif
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#ifndef EVT_OVERRIDE
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#define EVT_OVERRIDE 0xFFE02100
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#endif
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#ifndef ITABLE
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#define ITABLE 0x000FF000
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#endif
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#ifndef PROGRAM_STACK
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#define PROGRAM_STACK 0x000FF100
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000300
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#endif
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// Boot code
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BOOT :
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INIT_R_REGS(0); // Initialize Dregs
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INIT_P_REGS(0); // Initialize Pregs
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// CHECK_INIT(p5, 0x00BFFFFC);
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// CHECK_INIT(p5, 0xE0000000);
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include(symtable.inc)
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CHECK_INIT_DEF(p5);
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LD32(sp, 0x000FF200);
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LD32(p0, EVT); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R0 = -1; // Change this to mask interrupts (*)
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[ P0 ] = R0; // IMASK
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LD32_LABEL(p1, START);
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LD32(p0, EVT15);
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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CSYNC;
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RAISE 15; // after we RTI, INT 15 should be taken
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LD32_LABEL(r7, START);
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RETI = r7;
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NOP; // Workaround for Bug 217
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RTI;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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DUMMY:
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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//.code 0x200
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START :
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R7 = 0x0;
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R6 = 0x1;
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[ -- SP ] = RETI; // Enable Nested Interrupts
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CLI R1; // stop interrupt
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WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON TMPWR (active state)
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WR_MMR(TPERIOD, 0x00000050, p0, r0);
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WR_MMR(TCOUNT, 0x00000013, p0, r0);
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WR_MMR(TSCALE, 0x00000000, p0, r0);
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CSYNC;
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// Read the contents of the Timer
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RD_MMR(TPERIOD, p0, r2);
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CHECKREG(r2, 0x00000050);
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// RD_MMR(TCOUNT, p0, r3);
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// CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
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WR_MMR(TCNTL, 0x00000003, p0, r0); // enable Timer (TMPWR, TMREN)
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CSYNC;
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RD_MMR(TPERIOD, p0, r4);
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CHECKREG(r4, 0x00000050);
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// RD_MMR(TCNTL, p0, r5);
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// CHECKREG(r5, 0x0000000B); // INTERRUPT did happen
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WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
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CSYNC;
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NOP;
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WR_MMR(TCNTL, 0x00000001, p0, r0); // Turn ON Timer Power
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WR_MMR(TPERIOD, 0x00000015, p0, r0);
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WR_MMR(TCOUNT, 0x00000013, p0, r0);
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WR_MMR(TSCALE, 0x00000002, p0, r0);
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WR_MMR(TCNTL, 0x00000007, p0, r0); // Turn ON Timer (TAUTORLD=1)
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CSYNC;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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JUMP.S label4;
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R4.L = 0x1111; // Will be killed
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R4.H = 0x1111; // Will be killed
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NOP;
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NOP;
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NOP;
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label5: R5.H = 0x7777;
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R5.L = 0x7888;
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JUMP.S label6;
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R5.L = 0x1111; // Will be killed
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R5.H = 0x1111; // Will be killed
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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label4: R4.H = 0x5555;
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R4.L = 0x6666;
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NOP;
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JUMP.S label5;
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R5.L = 0x2222; // Will be killed
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R5.H = 0x2222; // Will be killed
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NOP;
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NOP;
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NOP;
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NOP;
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label6: R3.H = 0x7999;
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R3.L = 0x7aaa;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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// With auto reload
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// Read the contents of the Timer
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RD_MMR(TPERIOD, p0, r2);
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CHECKREG(r2, 0x00000015);
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// RD_MMR(TCNTL , p0, r3);
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// CHECKREG(r3, 0x0000000F);
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CHECKREG(r7, 0x00000000); // no interrupt being serviced
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WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
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CSYNC;
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STI R1;
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NOP;
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CHECKREG(r7, 0x00000001); // interrupt being serviced
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// WR_MMR(TCNTL, 0x00000000, p0, r0); // Turn OFF Timer
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// csync;
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NOP;
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dbg_pass; // Call Endtest Macro
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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RTN;
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XHANDLE: // Exception Handler 3
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RTX;
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HWHANDLE: // HW Error Handler 5
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RTI;
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THANDLE: // Timer Handler 6
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R7 = R7 + R6;
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RTI;
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I7HANDLE: // IVG 7 Handler
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RTI;
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I8HANDLE: // IVG 8 Handler
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RTI;
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I9HANDLE: // IVG 9 Handler
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RTI;
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I10HANDLE: // IVG 10 Handler
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RTI;
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I11HANDLE: // IVG 11 Handler
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RTI;
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I12HANDLE: // IVG 12 Handler
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RTI;
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I13HANDLE: // IVG 13 Handler
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RTI;
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I14HANDLE: // IVG 14 Handler
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RTI;
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I15HANDLE: // IVG 15 Handler
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R5 = RETI;
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P0 = R5;
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JUMP ( P0 );
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RTI;
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.section MEM_DATA_ADDR_1,"aw"
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.space (STACKSIZE);
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STACK:
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NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
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